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Searched refs:levels (Results 1 – 25 of 94) sorted by relevance

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/drivers/gpu/drm/radeon/
A Drv730_dpm.c244 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
247 table->ACPIState.levels[0].gen2XSP = in rv730_populate_smc_acpi_state()
251 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
252 table->ACPIState.levels[0].gen2PCIE = 0; in rv730_populate_smc_acpi_state()
310 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in rv730_populate_smc_acpi_state()
311 table->ACPIState.levels[2] = table->ACPIState.levels[0]; in rv730_populate_smc_acpi_state()
358 table->initialState.levels[0].seqValue = in rv730_populate_smc_initial_state()
363 &table->initialState.levels[0].vddc); in rv730_populate_smc_initial_state()
365 &table->initialState.levels[0].mvdd); in rv730_populate_smc_initial_state()
382 table->initialState.levels[1] = table->initialState.levels[0]; in rv730_populate_smc_initial_state()
[all …]
A Drv740_dpm.c337 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
338 table->ACPIState.levels[0].gen2PCIE = in rv740_populate_smc_acpi_state()
341 table->ACPIState.levels[0].gen2XSP = in rv740_populate_smc_acpi_state()
345 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
346 table->ACPIState.levels[0].gen2PCIE = 0; in rv740_populate_smc_acpi_state()
381 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_smc_acpi_state()
383 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; in rv740_populate_smc_acpi_state()
389 table->ACPIState.levels[0].sclk.sclk_value = 0; in rv740_populate_smc_acpi_state()
391 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in rv740_populate_smc_acpi_state()
392 table->ACPIState.levels[2] = table->ACPIState.levels[0]; in rv740_populate_smc_acpi_state()
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A Dcypress_dpm.c778 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
785 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
792 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
802 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
803 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
804 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
806 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
1325 table->initialState.levels[1] = table->initialState.levels[0]; in cypress_populate_smc_initial_state()
1326 table->initialState.levels[2] = table->initialState.levels[0]; in cypress_populate_smc_initial_state()
1464 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in cypress_populate_smc_acpi_state()
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A Dsumo_dpm.c1063 ps->levels[0].ss_divider_index = in sumo_patch_thermal_state()
1069 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1) in sumo_patch_thermal_state()
1070 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1; in sumo_patch_thermal_state()
1072 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) { in sumo_patch_thermal_state()
1074 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1; in sumo_patch_thermal_state()
1114 ps->levels[i].sclk = in sumo_apply_state_adjust_rules()
1123 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1) in sumo_apply_state_adjust_rules()
1124 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1; in sumo_apply_state_adjust_rules()
1126 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) { in sumo_apply_state_adjust_rules()
1128 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1; in sumo_apply_state_adjust_rules()
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A Drv770_dpm.c687 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
694 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
701 &smc_state->levels[2], in rv770_convert_power_state_to_smc()
944 &table->ACPIState.levels[0].vddc); in rv770_populate_smc_acpi_state()
953 table->ACPIState.levels[0].gen2XSP = 1; in rv770_populate_smc_acpi_state()
958 &table->ACPIState.levels[0].vddc); in rv770_populate_smc_acpi_state()
1001 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in rv770_populate_smc_acpi_state()
1002 table->ACPIState.levels[2] = table->ACPIState.levels[0]; in rv770_populate_smc_acpi_state()
1069 table->initialState.levels[0].seqValue = in rv770_populate_smc_initial_state()
1107 table->initialState.levels[1] = table->initialState.levels[0]; in rv770_populate_smc_initial_state()
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A Dtrinity_dpm.c1283 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1373 ps->levels[0].ds_divider_index = in trinity_patch_thermal_state()
1375 ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index; in trinity_patch_thermal_state()
1376 ps->levels[0].allow_gnb_slow = 1; in trinity_patch_thermal_state()
1378 ps->levels[0].display_wm = 0; in trinity_patch_thermal_state()
1379 ps->levels[0].vce_wm = in trinity_patch_thermal_state()
1519 ps->levels[i].sclk = in trinity_apply_state_adjust_rules()
1533 ps->levels[i].ds_divider_index = in trinity_apply_state_adjust_rules()
1536 ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index; in trinity_apply_state_adjust_rules()
1540 ps->levels[i].display_wm = in trinity_apply_state_adjust_rules()
[all …]
A Dkv_dpm.c1570 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1576 if ((new_ps->levels[0].sclk - in kv_set_valid_clock_range()
1579 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1985 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
1986 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
1995 ps->levels[i].sclk = table->entries[limit].clk; in kv_apply_state_adjust_rules()
2014 ps->levels[i].sclk = stable_p_state_sclk; in kv_apply_state_adjust_rules()
2376 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2412 struct kv_pl *pl = &ps->levels[index]; in kv_parse_pplib_clock_info()
2654 struct kv_pl *pl = &ps->levels[i]; in kv_dpm_print_power_state()
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A Dni_dpm.c2415 smc_state->levels[0].aT = cpu_to_be32(0); in ni_populate_smc_t()
2499 smc_state->levels[0].dpm2.MaxPS = 0; in ni_populate_power_containment_values()
2500 smc_state->levels[0].dpm2.NearTDPDec = 0; in ni_populate_power_containment_values()
2501 smc_state->levels[0].dpm2.AboveSafeInc = 0; in ni_populate_power_containment_values()
2502 smc_state->levels[0].dpm2.BelowSafeInc = 0; in ni_populate_power_containment_values()
2527 smc_state->levels[i].dpm2.MaxPS = in ni_populate_power_containment_values()
2532 smc_state->levels[i].stateFlags |= in ni_populate_power_containment_values()
2648 &smc_state->levels[i]); in ni_convert_power_state_to_smc()
2649 smc_state->levels[i].arbRefreshState = in ni_convert_power_state_to_smc()
2656 smc_state->levels[i].displayWatermark = in ni_convert_power_state_to_smc()
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/drivers/video/backlight/
A Dpwm_bl.c25 unsigned int *levels; member
80 if (pb->levels) in compute_duty_cycle()
199 if (!data->levels) in pwm_backlight_brightness_default()
257 if (!data->levels) in pwm_backlight_parse_dt()
261 data->levels, in pwm_backlight_parse_dt()
323 y1 = data->levels[i]; in pwm_backlight_parse_dt()
324 y2 = data->levels[i + 1]; in pwm_backlight_parse_dt()
341 data->levels = table; in pwm_backlight_parse_dt()
530 if (data->levels) { in pwm_backlight_probe()
531 pb->levels = data->levels; in pwm_backlight_probe()
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A Dled_bl.c20 unsigned int *levels; member
30 if (priv->levels) in led_bl_set_brightness()
31 bkl_brightness = priv->levels[level]; in led_bl_set_brightness()
138 u32 *levels = NULL; in led_bl_parse_levels() local
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels, in led_bl_parse_levels()
142 if (!levels) in led_bl_parse_levels()
146 levels, in led_bl_parse_levels()
157 if ((i && db > levels[i-1]) && db <= levels[i]) in led_bl_parse_levels()
162 priv->levels = levels; in led_bl_parse_levels()
A Dmp3309c.c63 unsigned int *levels; member
128 chip->pdata->levels[brightness], in mp3309c_bl_update_status()
129 chip->pdata->levels[chip->pdata->max_brightness]); in mp3309c_bl_update_status()
261 pdata->levels = devm_kcalloc(dev, num_levels, sizeof(*pdata->levels), GFP_KERNEL); in mp3309c_parse_fwnode()
262 if (!pdata->levels) in mp3309c_parse_fwnode()
266 pdata->levels, num_levels); in mp3309c_parse_fwnode()
271 pdata->levels[i] = i; in mp3309c_parse_fwnode()
/drivers/acpi/
A Dacpi_video.c317 *levels = NULL; in acpi_video_device_lcd_query_levels()
329 *levels = obj; in acpi_video_device_lcd_query_levels()
840 sizeof(*br->levels), in acpi_video_get_levels()
842 if (!br->levels) { in acpi_video_get_levels()
859 br->levels[count] = value; in acpi_video_get_levels()
873 if (br->levels[i] == br->levels[ACPI_VIDEO_AC_LEVEL]) in acpi_video_get_levels()
875 if (br->levels[i] == br->levels[ACPI_VIDEO_BATTERY_LEVEL]) in acpi_video_get_levels()
884 br->levels[i] = br->levels[i - level_ac_battery]; in acpi_video_get_levels()
983 kfree(br->levels); in acpi_video_init_brightness()
1792 union acpi_object *levels; in acpi_video_run_bcl_for_osi() local
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A Dpptt.c197 unsigned int *levels, unsigned int *split_levels) in acpi_count_levels() argument
200 acpi_find_cache_level(table_hdr, cpu_node, levels, split_levels, 0, 0); in acpi_count_levels()
626 int acpi_get_cache_info(unsigned int cpu, unsigned int *levels, in acpi_get_cache_info() argument
633 *levels = 0; in acpi_get_cache_info()
648 acpi_count_levels(table, cpu_node, levels, split_levels); in acpi_get_cache_info()
651 *levels, split_levels ? *split_levels : -1); in acpi_get_cache_info()
/drivers/thermal/intel/int340x_thermal/
A Dint3406_thermal.c60 acpi_level = d->br->levels[d->upper_limit - state]; in int3406_thermal_set_cur_state()
83 if (acpi_level <= d->br->levels[index]) in int3406_thermal_get_cur_state()
115 d->lower_limit = int3406_thermal_get_index(d->br->levels, in int3406_thermal_get_limit()
120 d->upper_limit = int3406_thermal_get_index(d->br->levels, in int3406_thermal_get_limit()
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
A Dvmm.c123 ctrl->levels[i].physAddress = pd->pt[0]->addr; in r535_mmu_vaspace_new()
124 ctrl->levels[i].size = BIT_ULL(desc->bits) * desc->size; in r535_mmu_vaspace_new()
125 ctrl->levels[i].aperture = 1; in r535_mmu_vaspace_new()
126 ctrl->levels[i].pageShift = page_shift; in r535_mmu_vaspace_new()
/drivers/base/
A Dcacheinfo.c331 unsigned int levels = 0, leaves, level; in init_of_cache_level() local
339 levels = 1; in init_of_cache_level()
351 if (level <= levels) in init_of_cache_level()
355 levels = level; in init_of_cache_level()
358 this_cpu_ci->num_levels = levels; in init_of_cache_level()
525 unsigned int levels = 0, split_levels = 0; in fetch_cache_info() local
531 ret = acpi_get_cache_info(cpu, &levels, &split_levels); in fetch_cache_info()
533 this_cpu_ci->num_levels = levels; in fetch_cache_info()
540 this_cpu_ci->num_leaves = levels + split_levels; in fetch_cache_info()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dfiji_smumgr.c1014 struct SMU73_Discrete_GraphicsLevel *levels = in fiji_populate_all_graphic_levels() local
1025 &levels[i]); in fiji_populate_all_graphic_levels()
1031 levels[i].DeepSleepDivId = 0; in fiji_populate_all_graphic_levels()
1035 levels[0].EnabledForActivity = 1; in fiji_populate_all_graphic_levels()
1052 levels[i].pcieDpmLevel = in fiji_populate_all_graphic_levels()
1230 struct SMU73_Discrete_MemoryLevel *levels = in fiji_populate_all_memory_levels() local
1240 &levels[i]); in fiji_populate_all_memory_levels()
1246 levels[0].EnabledForActivity = 1; in fiji_populate_all_memory_levels()
2555 struct SMU73_Discrete_GraphicsLevel *levels = in fiji_update_dpm_settings() local
2576 if (levels[i].ActivityLevel != in fiji_update_dpm_settings()
[all …]
A Dpolaris10_smumgr.c1050 struct SMU74_Discrete_GraphicsLevel *levels = in polaris10_populate_all_graphic_levels() local
1077 levels[i].DeepSleepDivId = 0; in polaris10_populate_all_graphic_levels()
1112 levels[i].pcieDpmLevel = in polaris10_populate_all_graphic_levels()
1143 levels[1].pcieDpmLevel = mid_pcie_level_enabled; in polaris10_populate_all_graphic_levels()
1219 struct SMU74_Discrete_MemoryLevel *levels = in polaris10_populate_all_memory_levels() local
1229 &levels[i]); in polaris10_populate_all_memory_levels()
2593 struct SMU74_Discrete_GraphicsLevel *levels = in polaris10_update_dpm_settings() local
2614 if (levels[i].ActivityLevel != in polaris10_update_dpm_settings()
2626 if (levels[i].UpHyst != setting->sclk_up_hyst || in polaris10_update_dpm_settings()
2628 levels[i].UpHyst = setting->sclk_up_hyst; in polaris10_update_dpm_settings()
[all …]
A Dvegam_smumgr.c878 struct SMU75_Discrete_GraphicsLevel *levels = in vegam_populate_all_graphic_levels() local
896 levels[i].UpHyst = (uint8_t) in vegam_populate_all_graphic_levels()
898 levels[i].DownHyst = (uint8_t) in vegam_populate_all_graphic_levels()
902 levels[i].DeepSleepDivId = 0; in vegam_populate_all_graphic_levels()
914 levels[i].EnabledForActivity = in vegam_populate_all_graphic_levels()
923 levels[i].pcieDpmLevel = in vegam_populate_all_graphic_levels()
1045 struct SMU75_Discrete_MemoryLevel *levels = in vegam_populate_all_memory_levels() local
1055 &levels[i]); in vegam_populate_all_memory_levels()
1060 levels[i].UpHyst = (uint8_t) in vegam_populate_all_memory_levels()
1062 levels[i].DownHyst = (uint8_t) in vegam_populate_all_memory_levels()
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/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu8_hwmgr.c1366 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()
1368 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()
1380 smu8_ps->levels[0] = data->boot_power_level; in smu8_dpm_patch_boot_state()
1402 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()
1408 smu8_ps->levels[index].dsDividerIndex = 5; in smu8_dpm_get_pp_table_entry_callback()
1409 smu8_ps->levels[index].ssDividerIndex = 5; in smu8_dpm_get_pp_table_entry_callback()
1623 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1627 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()
1628 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
1651 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()
[all …]
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dkv_dpm.c1808 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1814 if ((new_ps->levels[0].sclk - in kv_set_valid_clock_range()
2247 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
2248 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
2257 ps->levels[i].sclk = table->entries[limit].clk; in kv_apply_state_adjust_rules()
2276 ps->levels[i].sclk = stable_p_state_sclk; in kv_apply_state_adjust_rules()
2641 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2677 struct kv_pl *pl = &ps->levels[index]; in kv_parse_pplib_clock_info()
2894 struct kv_pl *pl = &ps->levels[i]; in kv_dpm_print_power_state()
2927 return requested_state->levels[0].sclk; in kv_dpm_get_sclk()
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/drivers/md/persistent-data/
A Ddm-btree.c208 return f->level < (info->levels - 1); in is_internal_level()
377 unsigned int level, last_level = info->levels - 1; in dm_btree_lookup()
384 for (level = 0; level < info->levels; level++) { in dm_btree_lookup()
479 for (level = 0; level < info->levels - 1u; level++) { in dm_btree_lookup_next()
1209 BUG_ON(info->levels > 1); in btree_get_overwrite_leaf()
1240 unsigned int level, index = -1, last_level = info->levels - 1; in insert()
1249 for (level = 0; level < (info->levels - 1); level++) { in insert()
1384 for (level = 0; level < info->levels; level++) { in dm_btree_find_key()
1386 level == info->levels - 1 ? NULL : &root); in dm_btree_find_key()
1460 BUG_ON(info->levels > 1); in dm_btree_walk()
/drivers/md/
A Ddm-verity-target.c331 if (likely(v->levels)) { in verity_hash_for_block()
346 for (i = v->levels - 1; i >= 0; i--) { in verity_hash_for_block()
646 for (i = v->levels - 2; i >= 0; i--) { in verity_prefetch_io()
1483 v->levels = 0; in verity_ctr()
1485 while (v->hash_per_block_bits * v->levels < 64 && in verity_ctr()
1487 (v->hash_per_block_bits * v->levels)) in verity_ctr()
1488 v->levels++; in verity_ctr()
1490 if (v->levels > DM_VERITY_MAX_LEVELS) { in verity_ctr()
1497 for (i = v->levels - 1; i >= 0; i--) { in verity_ctr()
/drivers/vfio/
A Dvfio_iommu_spapr_tce.c611 __u32 levels, in tce_iommu_create_table() argument
617 levels); in tce_iommu_create_table()
626 page_shift, window_size, levels, ptbl); in tce_iommu_create_table()
644 __u32 page_shift, __u64 window_size, __u32 levels, in tce_iommu_create_window() argument
673 page_shift, window_size, levels, &tbl); in tce_iommu_create_window()
892 info.ddw.levels = table_group->max_levels; in tce_iommu_ioctl()
1137 create.window_size, create.levels, in tce_iommu_ioctl()
/drivers/hv/
A DKconfig29 (VTLs). Virtual Trust Levels are hierarchical, with higher levels
30 being more privileged than lower levels. VTL0 is the least privileged

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