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Searched refs:memory_clock (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/radeon/
A Drv740_dpm.c93 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
104 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
186 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
204 memory_clock, false, &dividers); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
269 memory_clock); in rv740_populate_mclk_value()
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
408 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
412 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio()
415 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
A Drv770_dpm.h184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
A Dcypress_dpm.c577 memory_clock); in cypress_populate_mclk_value()
614 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument
620 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
622 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
627 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio()
629 else if (memory_clock > 135000) in cypress_get_mclk_frequency_ratio()
636 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
638 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
643 if (memory_clock < 40000) in cypress_get_mclk_frequency_ratio()
645 else if (memory_clock > 115000) in cypress_get_mclk_frequency_ratio()
[all …]
A Dcypress_dpm.h125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
A Dsi_dpm.h230 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
231 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
A Drv730_dpm.c117 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
133 memory_clock, false, &dividers); in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
A Dci_dpm.c2453 const u32 memory_clock, in ci_register_patching_mc_arb() argument
2465 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2469 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2745 u32 memory_clock, in ci_calculate_mclk_params() argument
2817 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2832 u32 memory_clock, in ci_populate_single_memory_level() argument
2842 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
2850 memory_clock, &memory_level->MinVddci); in ci_populate_single_memory_level()
2858 memory_clock, &memory_level->MinMvdd); in ci_populate_single_memory_level()
2868 memory_clock, in ci_populate_single_memory_level()
[all …]
A Drv770_dpm.c319 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument
330 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
332 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
388 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
412 memory_clock, false, &dividers); in rv770_populate_mclk_value()
419 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value()
446 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value()
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
A Dsi_dpm.c3760 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
3764 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
3766 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
3778 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
3780 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
3785 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
3787 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
4812 u32 memory_clock, in si_populate_mclk_value() argument
4858 freq_nom = memory_clock * 4; in si_populate_mclk_value()
4860 freq_nom = memory_clock * 2; in si_populate_mclk_value()
[all …]
A Dni_dpm.c2162 u32 memory_clock, in ni_populate_mclk_value() argument
2184 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2238 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value()
2261 memory_clock); in ni_populate_mclk_value()
2285 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Diceland_smumgr.c1046 uint32_t memory_clock, in iceland_calculate_mclk_params() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio()
1199 if (memory_clock < 10000) { in iceland_get_ddr3_mclk_frequency_ratio()
1229 uint32_t memory_clock, in iceland_populate_single_memory_level() argument
1252 memory_clock, in iceland_populate_single_memory_level()
1585 uint32_t memory_clock, in iceland_populate_memory_timing_parameters() argument
1595 engine_clock, memory_clock); in iceland_populate_memory_timing_parameters()
1729 const uint32_t memory_clock, in iceland_convert_mc_reg_table_entry_to_smc() argument
[all …]
A Dci_smumgr.c1025 uint32_t memory_clock, in ci_calculate_mclk_params() argument
1125 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1127 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1132 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio()
1147 if (memory_clock < 10000) in ci_get_ddr3_mclk_frequency_ratio()
1176 uint32_t memory_clock, in ci_populate_single_memory_level() argument
1197 memory_clock, in ci_populate_single_memory_level()
1206 memory_clock, in ci_populate_single_memory_level()
1624 uint32_t memory_clock, in ci_populate_memory_timing_parameters() argument
1764 const uint32_t memory_clock, in ci_convert_mc_reg_table_entry_to_smc() argument
[all …]
A Dtonga_smumgr.c789 uint32_t memory_clock, in tonga_calculate_mclk_params() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio()
948 if (memory_clock < 10000) in tonga_get_ddr3_mclk_frequency_ratio()
950 else if (memory_clock >= 80000) in tonga_get_ddr3_mclk_frequency_ratio()
961 uint32_t memory_clock, in tonga_populate_single_memory_level() argument
985 memory_clock, in tonga_populate_single_memory_level()
1460 uint32_t memory_clock, in tonga_populate_memory_timing_parameters() argument
2108 const uint32_t memory_clock, in tonga_convert_mc_reg_table_entry_to_smc() argument
[all …]
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dppatomctrl.h299 …t_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_in…
303 …et_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
320 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
A Dsmu7_hwmgr.c3403 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3468 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules()
3469 smu7_ps->performance_levels[0].memory_clock) in smu7_apply_state_adjust_rules()
3470 smu7_ps->performance_levels[1].memory_clock = in smu7_apply_state_adjust_rules()
3471 smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3799 uint32_t engine_clock, memory_clock; in smu7_get_pp_table_entry_callback_func_v0() local
3806 data->highest_mclk = memory_clock; in smu7_get_pp_table_entry_callback_func_v0()
3823 performance_level->memory_clock = memory_clock; in smu7_get_pp_table_entry_callback_func_v0()
4336 smu7_ps->performance_levels[0].memory_clock, in smu7_trim_dpm_states()
4709 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()
[all …]
A Dppatomctrl.c220 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument
233 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770()
903 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument
907 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum()
949 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument
957 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
A Dhardwaremanager.c391 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
401 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
A Dsmu7_hwmgr.h55 uint32_t memory_clock; member
A Dsmu10_hwmgr.c1122 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level()
1125 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
A Dsmu8_hwmgr.c1635 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level()
1637 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dhardwaremanager.h272 uint32_t memory_clock; member
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c4307 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
4309 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
4321 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
4323 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
4326 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4328 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
4330 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
5382 u32 memory_clock, in si_populate_mclk_value() argument
5428 freq_nom = memory_clock * 4; in si_populate_mclk_value()
5430 freq_nom = memory_clock * 2; in si_populate_mclk_value()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h269 uint32_t memory_clock; member
424 uint32_t memory_clock; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsienna_cichlid_ppt.c1839 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1863 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
A Dnavi10_ppt.c2137 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
2161 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()

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