| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.c | 78 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
95 bool p_state_change_support; in dcn201_update_clocks() local
134 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn201_update_clocks()
135 …should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_cha… in dcn201_update_clocks()
136 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn201_update_clocks()
137 clk_mgr_base->clks.p_state_change_support = p_state_change_support; in dcn201_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 115 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
209 bool p_state_change_support; in dcn3_update_clocks() local
249 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn3_update_clocks()
250 p_state_change_support = new_clocks->p_state_change_support; in dcn3_update_clocks()
253 if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) { in dcn3_update_clocks()
259 …should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_cha… in dcn3_update_clocks()
261 clk_mgr_base->clks.p_state_change_support = p_state_change_support; in dcn3_update_clocks()
264 if (!clk_mgr_base->clks.p_state_change_support) { in dcn3_update_clocks()
282 if (clk_mgr_base->clks.p_state_change_support && in dcn3_update_clocks()
364 if (clk_mgr_base->clks.p_state_change_support) in dcn3_set_hard_min_memclk()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 231 bool p_state_change_support; in dcn2_update_clocks() local
282 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn2_update_clocks()
283 …should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_cha… in dcn2_update_clocks()
284 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn2_update_clocks()
285 clk_mgr_base->clks.p_state_change_support = p_state_change_support; in dcn2_update_clocks()
287 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); in dcn2_update_clocks()
407 clk_mgr->clks.p_state_change_support = true; in dcn2_init_clocks()
486 else if (a->p_state_change_support != b->p_state_change_support) in dcn2_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr.c | 175 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks()
543 if (!new_clocks->p_state_change_support) { in dcn32_auto_dpm_test_log()
636 bool p_state_change_support; in dcn32_update_clocks() local
696 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn32_update_clocks()
705 p_state_change_support = new_clocks->p_state_change_support; in dcn32_update_clocks()
706 …should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_cha… in dcn32_update_clocks()
708 clk_mgr_base->clks.p_state_change_support = p_state_change_support; in dcn32_update_clocks()
711 if (!clk_mgr_base->clks.p_state_change_support) { in dcn32_update_clocks()
753 if (clk_mgr_base->clks.p_state_change_support && in dcn32_update_clocks()
1002 if (clk_mgr_base->clks.p_state_change_support) in dcn32_set_hard_min_memclk()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| A D | dcn401_clk_mgr.c | 228 clk_mgr_base->clks.p_state_change_support = true; in dcn401_init_clocks()
445 if (!new_clocks->p_state_change_support) in dcn401_auto_dpm_test_log()
899 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence()
900 uclk_p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn401_build_update_bandwidth_clocks_sequence()
902 clk_mgr_base->clks.p_state_change_support = uclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence()
906 if (clk_mgr_base->clks.p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence()
934 if (clk_mgr_base->clks.p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence()
943 if (clk_mgr_base->clks.p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence()
1344 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_set_hard_min_memclk()
1348 new_clocks.p_state_change_support = true; in dcn401_set_hard_min_memclk()
[all …]
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_trace.h | 503 __field(int, p_state_change_support)
521 __entry->p_state_change_support = clk->p_state_change_support;
546 __entry->p_state_change_support,
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| A D | amdgpu_dm_helpers.c | 1324 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 75 clocks->p_state_change_support = true; in dcn401_initialize_min_clocks()
1360 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_prepare_bandwidth() local
1364 if (p_state_change_support) { in dcn401_prepare_bandwidth()
1366 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn401_prepare_bandwidth()
1407 if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { in dcn401_prepare_bandwidth()
1410 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn401_prepare_bandwidth()
1628 if ((!dc->clk_mgr->clks.p_state_change_support || in dcn401_hardware_release()
1634 dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn401_hardware_release()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 758 clocks->p_state_change_support = true; in dcn32_initialize_min_clocks()
1789 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn32_prepare_bandwidth() local
1795 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn32_prepare_bandwidth()
1812 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn32_prepare_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1171 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
1214 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn20_calculate_dlg_params()
1242 context->bw_ctx.bw.dcn.clk.p_state_change_support, in dcn20_calculate_dlg_params()
2103 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn20_validate_bandwidth_fp()
2107 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; in dcn20_validate_bandwidth_fp()
2116 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn20_validate_bandwidth_fp()
2119 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn20_validate_bandwidth_fp()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 561 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn31_calculate_wm_and_dlg_fp()
571 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn31_calculate_wm_and_dlg_fp()
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| A D | dcn20_hubbub.c | 616 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) in hubbub2_program_watermarks()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 1167 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use || in dcn30_hardware_release()
1191 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn30_prepare_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 449 clk_mgr->clks.p_state_change_support = true; in rn_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.c | 381 clk_mgr->clks.p_state_change_support = true; in vg_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 181 if (!new_clocks->p_state_change_support) in dcn315_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 304 clk_mgr->clks.p_state_change_support = true; in dcn31_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 5826 bool p_state_change_support; in dc_enable_dcmode_clk_limit() local
5837 p_state_change_support = dc->clk_mgr->clks.p_state_change_support; in dc_enable_dcmode_clk_limit()
5840 if (p_state_change_support) { in dc_enable_dcmode_clk_limit()
5850 if (p_state_change_support) { in dc_enable_dcmode_clk_limit()
6371 profile.power_level = !context->bw_ctx.bw.dcn.clk.p_state_change_support; in dc_get_power_profile_for_dc_state()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 191 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported; in dml2_copy_clocks_to_dc_state()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 192 clk_mgr->clks.p_state_change_support = true; in dcn314_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 661 bool p_state_change_support; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 1665 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn32_calculate_dlg_params()
1672 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn32_calculate_dlg_params()
1774 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn32_calculate_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 1162 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 617 clk_mgr->clks.p_state_change_support = true; in init_clk_states()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1814 return !context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn315_get_power_profile()
|