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Searched refs:range_bpg_offset (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc_1_2.c301 (rc[0].range_bpg_offset << 0) | in dpu_hw_dsc_config_thresh_1_2()
302 (rc[1].range_bpg_offset << 6) | in dpu_hw_dsc_config_thresh_1_2()
303 (rc[2].range_bpg_offset << 12) | in dpu_hw_dsc_config_thresh_1_2()
304 (rc[3].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
305 (rc[4].range_bpg_offset << 24)); in dpu_hw_dsc_config_thresh_1_2()
320 (rc[5].range_bpg_offset << 0) | in dpu_hw_dsc_config_thresh_1_2()
321 (rc[6].range_bpg_offset << 6) | in dpu_hw_dsc_config_thresh_1_2()
322 (rc[7].range_bpg_offset << 12) | in dpu_hw_dsc_config_thresh_1_2()
323 (rc[8].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
324 (rc[9].range_bpg_offset << 24)); in dpu_hw_dsc_config_thresh_1_2()
[all …]
A Ddpu_hw_dsc.c156 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); in dpu_hw_dsc_config_thresh()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c331 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
336 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
339 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
344 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, in dsc_write_to_registers()
347 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); in dsc_write_to_registers()
352 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, in dsc_write_to_registers()
355 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); in dsc_write_to_registers()
360 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, in dsc_write_to_registers()
363 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); in dsc_write_to_registers()
368 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c252 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()
1294 vdsc_cfg->rc_range_params[i].range_bpg_offset = in drm_dsc_setup_rc_params()
1295 rc_params->rc_range_params[i].range_bpg_offset & in drm_dsc_setup_rc_params()
1546 … rp[0].range_bpg_offset, rp[1].range_bpg_offset, rp[2].range_bpg_offset, rp[3].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1547 … rp[4].range_bpg_offset, rp[5].range_bpg_offset, rp[6].range_bpg_offset, rp[7].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1548 …rp[8].range_bpg_offset, rp[9].range_bpg_offset, rp[10].range_bpg_offset, rp[11].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1549 rp[12].range_bpg_offset, rp[13].range_bpg_offset, rp[14].range_bpg_offset); in drm_dsc_dump_config_rc_params()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c167 u8 range_bpg_offset; in calculate_rc_params() local
173 range_bpg_offset = ofs_und4[buf_i]; in calculate_rc_params()
184 range_bpg_offset = ofs_und8[buf_i]; in calculate_rc_params()
186 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
187 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; in calculate_rc_params()
215 u8 range_bpg_offset; in calculate_rc_params() local
221 range_bpg_offset = ofs_und6[buf_i]; in calculate_rc_params()
232 range_bpg_offset = ofs_und15[buf_i]; in calculate_rc_params()
234 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
235 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; in calculate_rc_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c709 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
714 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
717 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
722 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, in dsc_write_to_registers()
725 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); in dsc_write_to_registers()
730 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, in dsc_write_to_registers()
733 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); in dsc_write_to_registers()
738 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, in dsc_write_to_registers()
741 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); in dsc_write_to_registers()
746 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/dsc/
A Ddscc_types.h38 int range_bpg_offset; member
A Drc_calc_dpi.c87 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; in copy_rc_to_cfg()

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