Searched refs:rptr_offset (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_dcn20.c | 322 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn20_set_outbox1_rptr() argument
328 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn20_set_outbox1_rptr()
344 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn20_set_outbox0_rptr() argument
346 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn20_set_outbox0_rptr()
|
| A D | dmub_dcn31.c | 282 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn31_set_outbox1_rptr() argument
288 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn31_set_outbox1_rptr()
407 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn31_set_outbox0_rptr() argument
409 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn31_set_outbox0_rptr()
|
| A D | dmub_dcn35.c | 318 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn35_set_outbox1_rptr() argument
324 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn35_set_outbox1_rptr()
445 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn35_set_outbox0_rptr() argument
447 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn35_set_outbox0_rptr()
|
| A D | dmub_dcn32.c | 306 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn32_set_outbox1_rptr() argument
312 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn32_set_outbox1_rptr()
410 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn32_set_outbox0_rptr() argument
412 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn32_set_outbox0_rptr()
|
| A D | dmub_dcn20.h | 217 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
224 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
| A D | dmub_dcn401.c | 298 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn401_set_outbox1_rptr() argument
304 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn401_set_outbox1_rptr()
404 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) in dmub_dcn401_set_outbox0_rptr() argument
406 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn401_set_outbox0_rptr()
|
| A D | dmub_dcn31.h | 219 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
250 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
| A D | dmub_dcn32.h | 226 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
253 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
| A D | dmub_dcn35.h | 239 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
268 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
| A D | dmub_dcn401.h | 236 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
263 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
| /drivers/gpu/drm/amd/display/dmub/ |
| A D | dmub_srv.h | 440 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);
447 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);
|
Completed in 26 milliseconds