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Searched refs:src_clk (Results 1 – 8 of 8) sorted by relevance

/drivers/spi/
A Dspi-s3c64xx.c209 struct clk *src_clk; member
751 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); in s3c64xx_spi_config()
754 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; in s3c64xx_spi_config()
1017 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); in s3c64xx_spi_setup()
1027 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1037 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1338 if (IS_ERR(sdd->src_clk)) in s3c64xx_spi_probe()
1339 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), in s3c64xx_spi_probe()
1461 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1479 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
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A Dspi-sprd.c156 u32 src_clk; member
188 ss->src_clk); in sprd_spi_transfer_max_timeout()
657 u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1; in sprd_spi_set_speed()
660 ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1); in sprd_spi_set_speed()
882 ss->src_clk = clk_get_rate(clk_spi); in sprd_spi_clk_init()
884 ss->src_clk = SPRD_SPI_DEFAULT_SOURCE; in sprd_spi_clk_init()
946 sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1, in sprd_spi_probe()
/drivers/watchdog/
A Ds3c2410_wdt.c191 struct clk *src_clk; /* for WDT counter */ member
407 return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk); in s3c2410wdt_get_freq()
800 wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src"); in s3c2410wdt_probe()
801 if (IS_ERR(wdt->src_clk)) in s3c2410wdt_probe()
802 return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n"); in s3c2410wdt_probe()
/drivers/i2c/busses/
A Di2c-sprd.c84 u32 src_clk; member
323 u32 apb_clk = i2c_dev->src_clk; in sprd_i2c_set_clk()
465 i2c_dev->src_clk = clk_get_rate(clk_i2c); in sprd_i2c_clk_init()
467 i2c_dev->src_clk = 26000000; in sprd_i2c_clk_init()
470 i2c_dev->adap.nr, i2c_dev->src_clk); in sprd_i2c_clk_init()
/drivers/net/ethernet/intel/idpf/
A Didpf_ptp.c134 u64 *src_clk) in idpf_ptp_read_src_clk_reg_mailbox() argument
149 *src_clk = clk_time.dev_clk_time_ns; in idpf_ptp_read_src_clk_reg_mailbox()
163 static int idpf_ptp_read_src_clk_reg(struct idpf_adapter *adapter, u64 *src_clk, in idpf_ptp_read_src_clk_reg() argument
170 return idpf_ptp_read_src_clk_reg_mailbox(adapter, sts, src_clk); in idpf_ptp_read_src_clk_reg()
172 *src_clk = idpf_ptp_read_src_clk_reg_direct(adapter, sts); in idpf_ptp_read_src_clk_reg()
/drivers/input/serio/
A Dsun4i-ps2.c143 u32 src_clk = 0; in sun4i_ps2_open() local
160 src_clk = clk_get_rate(drvdata->clk); in sun4i_ps2_open()
162 clk_scdf = src_clk / PS2_SAMPLE_CLK - 1; in sun4i_ps2_open()
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c137 struct clk *src_clk; member
253 msm_host->src_clk = msm_clk_get(pdev, "src"); in dsi_clk_init_v2()
255 if (IS_ERR(msm_host->src_clk)) { in dsi_clk_init_v2()
256 ret = PTR_ERR(msm_host->src_clk); in dsi_clk_init_v2()
259 msm_host->src_clk = NULL; in dsi_clk_init_v2()
495 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); in dsi_link_clk_set_rate_v2()
526 ret = clk_prepare_enable(msm_host->src_clk); in dsi_link_clk_enable_v2()
541 clk_disable_unprepare(msm_host->src_clk); in dsi_link_clk_enable_v2()
563 clk_disable_unprepare(msm_host->src_clk); in dsi_link_clk_disable_v2()
/drivers/mmc/host/
A Dmtk-sd.c496 struct clk *src_clk; /* msdc source clock */ member
928 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
940 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
2912 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2913 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2914 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2937 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
3053 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()

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