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Searched refs:ull (Results 1 – 25 of 49) sorted by relevance

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/drivers/clk/imx/
A Dclk-pllv1.c56 unsigned long long ull; in clk_pllv1_recalc_rate() local
98 ull = (unsigned long long)rate * mfn_abs; in clk_pllv1_recalc_rate()
100 do_div(ull, mfd + 1); in clk_pllv1_recalc_rate()
103 ull = (rate * mfi) - ull; in clk_pllv1_recalc_rate()
105 ull = (rate * mfi) + ull; in clk_pllv1_recalc_rate()
107 return ull; in clk_pllv1_recalc_rate()
/drivers/net/ethernet/marvell/octeontx2/nic/
A Dcn20k.c116 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull); in cn20k_enable_pfvf_mbox_intr()
117 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull); in cn20k_enable_pfvf_mbox_intr()
118 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull); in cn20k_enable_pfvf_mbox_intr()
119 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull); in cn20k_enable_pfvf_mbox_intr()
138 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(0), ~0ull); in cn20k_disable_pfvf_mbox_intr()
139 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(1), ~0ull); in cn20k_disable_pfvf_mbox_intr()
140 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(0), ~0ull); in cn20k_disable_pfvf_mbox_intr()
143 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull); in cn20k_disable_pfvf_mbox_intr()
144 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull); in cn20k_disable_pfvf_mbox_intr()
147 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull); in cn20k_disable_pfvf_mbox_intr()
[all …]
A Dotx2_pf.c691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); in otx2_enable_pfvf_mbox_intr()
692 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); in otx2_enable_pfvf_mbox_intr()
711 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); in otx2_disable_pfvf_mbox_intr()
712 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); in otx2_disable_pfvf_mbox_intr()
714 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); in otx2_disable_pfvf_mbox_intr()
719 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); in otx2_disable_pfvf_mbox_intr()
/drivers/crypto/cavium/cpt/
A Dcptpf_main.c94 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); in cpt_disable_mbox_interrupts()
100 cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); in cpt_disable_ecc_interrupts()
106 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); in cpt_disable_exec_interrupts()
119 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); in cpt_enable_mbox_interrupts()
429 CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull); in cpt_unload_microcode()
A Dcptpf_mbox.c23 mbx->data = 0ull; in cpt_mbox_send_ack()
/drivers/infiniband/core/
A Dpacker.c101 mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); in ib_pack()
180 mask = (~0ull >> (64 - desc[i].size_bits)) << shift; in ib_unpack()
/drivers/crypto/marvell/octeontx/
A Dotx_cptpf_mbox.c89 mbx->data = 0ull; in otx_cpt_mbox_send_ack()
98 mbx->data = 0ull; in otx_cptpf_mbox_send_nack()
A Dotx_cptpf_main.c20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0)); in otx_cpt_disable_mbox_interrupts()
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0)); in otx_cpt_enable_mbox_interrupts()
/drivers/gpu/drm/xe/
A Dxe_gt_sriov_pf_debugfs.c141 if (val > (TYPE)~0ull) \
205 if (val > (TYPE)~0ull) \
261 if (val > (u32)~0ull) in set_threshold()
/drivers/gpu/drm/imagination/
A Dpvr_device_info.c66 u64 invalid_mask = ~0ull << (mapping_max & 63); in pvr_device_info_set_common()
232 u64 invalid_mask = ~0ull << (mapping_max & 63); in pvr_device_info_set_features()
A Dpvr_params.c95 0ull); \
/drivers/virt/nitro_enclaves/
A Dne_misc_dev_test.c6 #define INVALID_VALUE (~0ull)
/drivers/gpu/drm/xe/display/
A Dxe_fb_pin.c105 dpt_size, ~0ull, in __xe_pin_fb_vma_dpt()
113 dpt_size, ~0ull, in __xe_pin_fb_vma_dpt()
121 dpt_size, ~0ull, in __xe_pin_fb_vma_dpt()
/drivers/gpu/drm/panthor/
A Dpanthor_mmu.h75 #define PANTHOR_VM_KERNEL_AUTO_VA ~0ull
/drivers/infiniband/hw/hfi1/
A Dchip.c114 #define LRH_BTH_QW 0ull
123 #define LRH_SC_QW 0ull
128 #define LRH_SC_VALUE 0ull
157 #define L2_TYPE_QW 0ull
166 #define L4_TYPE_BIT_OFFSET 0ull
635 /* 0*/ FLAG_ENTRY0("Reserved", 0ull),
6805 freeze ? ALL_FROZE : 0ull); in wait_for_freeze_status()
13628 write_csr(dd, CCE_ERR_CLEAR, ~0ull); in reset_cce_csrs()
14634 write_csr(dd, RCV_ERR_MASK, ~0ull); in init_rxe()
14672 write_csr(dd, CCE_ERR_MASK, ~0ull); in init_other()
[all …]
/drivers/misc/ocxl/
A Dlink.c27 #define SPA_CFG_XLAT_hpt (0ull << (63-6)) /* Hashed page table (HPT) mode */
738 0ull, in ocxl_link_remove_pe()
/drivers/edac/
A Dskx_common.c511 if (size == ~0ull) in skx_get_nvdimm_info()
528 return (size == 0 || size == ~0ull) ? 0 : 1; in skx_get_nvdimm_info()
/drivers/infiniband/ulp/srp/
A Dib_srp.c3328 unsigned long long ull; in srp_parse_options() local
3354 ret = kstrtoull(p, 16, &ull); in srp_parse_options()
3360 target->id_ext = cpu_to_be64(ull); in srp_parse_options()
3370 ret = kstrtoull(p, 16, &ull); in srp_parse_options()
3376 target->ioc_guid = cpu_to_be64(ull); in srp_parse_options()
3413 ret = kstrtoull(p, 16, &ull); in srp_parse_options()
3419 target->ib_cm.service_id = cpu_to_be64(ull); in srp_parse_options()
3542 ret = kstrtoull(p, 16, &ull); in srp_parse_options()
3548 target->initiator_ext = cpu_to_be64(ull); in srp_parse_options()
/drivers/firmware/
A Ddmi_scan.c455 bytes = ~0ull; in save_mem_devices()
1180 return ~0ull; in dmi_memdev_size()
/drivers/net/ethernet/mellanox/mlx4/
A Den_main.c305 err = mlx4_mr_alloc(mdev->dev, mdev->priv_pdn, 0, ~0ull, in mlx4_en_probe()
/drivers/misc/genwqe/
A Dcard_ddcb.c1093 queue->ddcb_daddr = 0ull; in setup_ddcb_queue()
1116 queue->ddcb_daddr = 0ull; in free_ddcb_queue()
/drivers/gpu/drm/vc4/
A Dvc4_v3d.c204 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true); in vc4_v3d_get_bin_slot()
A Dvc4_gem.c418 if (timeout_ns != ~0ull) { in vc4_wait_for_seqno()
938 if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) { in vc4_wait_for_seqno_ioctl_helper()
/drivers/infiniband/hw/mlx4/
A Dmr.c68 ~0ull, convert_access(acc), 0, 0, &mr->mmr); in mlx4_ib_get_dma_mr()
/drivers/net/ethernet/marvell/octeon_ep_vf/
A Doctep_vf_mbox.c117 u64 reg_val = 0ull; in __octep_vf_mbox_send_cmd()

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