| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 1491 new_pipe->update_flags.raw = 0; in dcn20_detect_pipe_changes() 1509 new_pipe->update_flags.bits.odm = 1; in dcn20_detect_pipe_changes() 1757 if (pipe_ctx->update_flags.bits.mpcc in dcn20_update_dchubp_dpp() 1793 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || in dcn20_update_dchubp_dpp() 1805 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed in dcn20_update_dchubp_dpp() 1929 pipe_ctx->update_flags.bits.odm || in dcn20_program_pipe() 1941 if (pipe_ctx->update_flags.bits.odm) in dcn20_program_pipe() 2146 pipe->update_flags.bits.odm && in dcn20_program_front_end_for_ctx() 2184 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) in dcn20_program_front_end_for_ctx() 2185 || pipe->stream->update_flags.raw) in dcn20_program_front_end_for_ctx() [all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 1967 pipe_ctx->update_flags.bits.odm || in dcn401_program_pipe() 1979 if (pipe_ctx->update_flags.bits.odm) in dcn401_program_pipe() 2014 pipe_ctx->update_flags.bits.enable)) in dcn401_program_pipe() 2033 if (pipe_ctx->update_flags.bits.enable in dcn401_program_pipe() 2186 pipe->update_flags.bits.odm && in dcn401_program_front_end_for_ctx() 2224 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) in dcn401_program_front_end_for_ctx() 2225 || pipe->stream->update_flags.raw) in dcn401_program_front_end_for_ctx() 2446 new_pipe->update_flags.raw = 0; in dcn401_detect_pipe_changes() 2464 new_pipe->update_flags.bits.odm = 1; in dcn401_detect_pipe_changes() 2472 new_pipe->update_flags.bits.mpcc = 1; in dcn401_detect_pipe_changes() [all …]
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| /drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ |
| A D | csum.c | 11 u32 update_flags, in csum_offload_supported() argument 26 if (update_flags & ~prot_flags) { in csum_offload_supported() 31 update_flags); in csum_offload_supported()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 2618 union surface_update_flags *update_flags = &u->surface->update_flags; in get_plane_info_update_type() local 2667 update_flags->bits.dcc_change = 1; in get_plane_info_update_type() 2676 update_flags->bits.bpp_change = 1; in get_plane_info_update_type() 2712 union surface_update_flags *update_flags = &u->surface->update_flags; in get_scaling_info_update_type() local 2755 if (update_flags->bits.clock_change in get_scaling_info_update_type() 2772 union surface_update_flags *update_flags = &u->surface->update_flags; in det_surface_update() local 2775 update_flags->raw = 0xFFFFFFFF; in det_surface_update() 2822 update_flags->bits.lut_3d = 1; in det_surface_update() 2826 update_flags->bits.hdr_mult = 1; in det_surface_update() 2851 if (update_flags->bits.lut_3d && in det_surface_update() [all …]
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| A D | dc_hw_sequencer.c | 786 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) { in hwss_build_fast_sequence() 792 …gram_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) { in hwss_build_fast_sequence() 799 … if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) { in hwss_build_fast_sequence() 815 …if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_c… in hwss_build_fast_sequence() 823 …if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_c… in hwss_build_fast_sequence() 828 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) { in hwss_build_fast_sequence() 833 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) { in hwss_build_fast_sequence() 839 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { in hwss_build_fast_sequence() 854 if (current_mpc_pipe->stream->update_flags.bits.out_csc) { in hwss_build_fast_sequence() 912 current_mpc_pipe->plane_state->update_flags.bits.addr_update && in hwss_build_fast_sequence()
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| /drivers/s390/char/ |
| A D | con3270.c | 211 tp->update_flags |= TTY_UPDATE_INPUT; in tty3270_update_prompt() 309 tp->update_flags = TTY_UPDATE_ALL; in tty3270_write_callback() 575 if (tp->update_flags) in tty3270_update() 633 tp->update_flags = TTY_UPDATE_ALL; in tty3270_redraw() 703 tp->update_flags = TTY_UPDATE_ALL; in tty3270_read_tasklet() 788 tp->update_flags = TTY_UPDATE_ALL; in tty3270_activate() 821 tp->update_flags = TTY_UPDATE_ALL; in tty3270_irq() 1010 tp->update_flags = TTY_UPDATE_ALL; in tty3270_resize() 1930 tp->update_flags = TTY_UPDATE_ALL; in tty3270_hangup() 2126 tp->update_flags = TTY_UPDATE_ALL; in con3270_notify() [all …]
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| /drivers/hid/ |
| A D | hid-nvidia-shield.c | 217 unsigned long update_flags; member 328 if (test_and_clear_bit(THUNDERSTRIKE_FW_VERSION_UPDATE, &ts->update_flags)) { in thunderstrike_hostcmd_req_work_handler() 334 if (test_and_clear_bit(THUNDERSTRIKE_LED_UPDATE, &ts->update_flags)) { in thunderstrike_hostcmd_req_work_handler() 341 if (test_and_clear_bit(THUNDERSTRIKE_POWER_SUPPLY_STATS_UPDATE, &ts->update_flags)) { in thunderstrike_hostcmd_req_work_handler() 351 if (test_and_clear_bit(THUNDERSTRIKE_BOARD_INFO_UPDATE, &ts->update_flags)) { in thunderstrike_hostcmd_req_work_handler() 357 if (test_and_clear_bit(THUNDERSTRIKE_HAPTICS_UPDATE, &ts->update_flags)) { in thunderstrike_hostcmd_req_work_handler() 372 set_bit(THUNDERSTRIKE_FW_VERSION_UPDATE, &ts->update_flags); in thunderstrike_request_firmware_version() 378 set_bit(THUNDERSTRIKE_BOARD_INFO_UPDATE, &ts->update_flags); in thunderstrike_request_board_info() 392 set_bit(THUNDERSTRIKE_HAPTICS_UPDATE, &ts->update_flags); in thunderstrike_update_haptics() 452 set_bit(THUNDERSTRIKE_LED_UPDATE, &ts->update_flags); in thunderstrike_led_set_brightness() [all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 2959 if (plane_state->update_flags.bits.full_update) { in dcn10_update_dchubp_dpp() 3014 if (plane_state->update_flags.bits.full_update) { in dcn10_update_dchubp_dpp() 3031 if (plane_state->update_flags.bits.full_update || in dcn10_update_dchubp_dpp() 3032 plane_state->update_flags.bits.bpp_change) in dcn10_update_dchubp_dpp() 3035 if (plane_state->update_flags.bits.full_update || in dcn10_update_dchubp_dpp() 3040 if (plane_state->update_flags.bits.full_update || in dcn10_update_dchubp_dpp() 3043 plane_state->update_flags.bits.scaling_change || in dcn10_update_dchubp_dpp() 3048 if (plane_state->update_flags.bits.full_update || in dcn10_update_dchubp_dpp() 3049 plane_state->update_flags.bits.scaling_change || in dcn10_update_dchubp_dpp() 3081 plane_state->update_flags.bits.dcc_change || in dcn10_update_dchubp_dpp() [all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| A D | dce60_hwseq.c | 335 if (pipe_ctx->plane_state->update_flags.bits.full_update || in dce60_program_front_end_for_pipe() 336 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || in dce60_program_front_end_for_pipe() 337 pipe_ctx->plane_state->update_flags.bits.gamma_change) in dce60_program_front_end_for_pipe() 340 if (pipe_ctx->plane_state->update_flags.bits.full_update) in dce60_program_front_end_for_pipe()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 1461 phantom_pipe->update_flags.raw = 0; in dcn32_apply_update_flags_for_phantom() 1463 phantom_pipe->update_flags.bits.enable = 1; in dcn32_apply_update_flags_for_phantom() 1464 phantom_pipe->update_flags.bits.mpcc = 1; in dcn32_apply_update_flags_for_phantom() 1465 phantom_pipe->update_flags.bits.dppclk = 1; in dcn32_apply_update_flags_for_phantom() 1467 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; in dcn32_apply_update_flags_for_phantom() 1468 phantom_pipe->update_flags.bits.gamut_remap = 1; in dcn32_apply_update_flags_for_phantom() 1469 phantom_pipe->update_flags.bits.scaler = 1; in dcn32_apply_update_flags_for_phantom() 1470 phantom_pipe->update_flags.bits.viewport = 1; in dcn32_apply_update_flags_for_phantom() 1471 phantom_pipe->update_flags.bits.det_size = 1; in dcn32_apply_update_flags_for_phantom() 1473 phantom_pipe->update_flags.bits.odm = 1; in dcn32_apply_update_flags_for_phantom() [all …]
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_trace.h | 387 int update_flags), 388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags), 419 __field(unsigned int, update_flags) 451 __entry->update_flags = update_flags; 485 __entry->update_flags
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_trace.h | 32 pipe_ctx->update_flags.raw); \
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| A D | dc_stream.h | 308 union stream_update_flags update_flags; member
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| A D | dc.h | 1420 union surface_update_flags update_flags; member
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| A D | bnx2x_sp.c | 5164 ¶ms->update_flags); in bnx2x_q_fill_update_data() 5171 ¶ms->update_flags); in bnx2x_q_fill_update_data() 5192 ¶ms->update_flags); in bnx2x_q_fill_update_data() 5197 ¶ms->update_flags); in bnx2x_q_fill_update_data() 5208 ¶ms->update_flags); in bnx2x_q_fill_update_data() 5558 &update_params->update_flags) && in bnx2x_queue_chk_transition() 5560 &update_params->update_flags)) in bnx2x_queue_chk_transition() 5585 &update_params->update_flags) && in bnx2x_queue_chk_transition() 5587 &update_params->update_flags)) in bnx2x_queue_chk_transition() 5620 &update_params->update_flags) && in bnx2x_queue_chk_transition() [all …]
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| A D | bnx2x_sriov.c | 2376 &q_params.params.update.update_flags); in bnx2x_set_pf_tx_switching() 2379 &q_params.params.update.update_flags); in bnx2x_set_pf_tx_switching() 2905 &update_params->update_flags); in bnx2x_set_vf_vlan() 2907 &update_params->update_flags); in bnx2x_set_vf_vlan() 2914 &update_params->update_flags); in bnx2x_set_vf_vlan() 2916 &update_params->update_flags); in bnx2x_set_vf_vlan() 2922 &update_params->update_flags); in bnx2x_set_vf_vlan() 2924 &update_params->update_flags); in bnx2x_set_vf_vlan() 2995 &update_params->update_flags); in bnx2x_set_vf_spoofchk() 2998 &update_params->update_flags); in bnx2x_set_vf_spoofchk() [all …]
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| A D | bnx2x_sp.h | 913 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ member
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| A D | bnx2x_main.c | 5398 &q_update_params->update_flags); in bnx2x_after_function_update() 5400 &q_update_params->update_flags); in bnx2x_after_function_update() 15234 &q_params.params.update.update_flags); in bnx2x_enable_ptp_packets() 15236 &q_params.params.update.update_flags); in bnx2x_enable_ptp_packets()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_vm.c | 1337 uint64_t update_flags = flags; in amdgpu_vm_bo_update() local 1343 update_flags &= ~AMDGPU_PTE_READABLE; in amdgpu_vm_bo_update() 1345 update_flags &= ~AMDGPU_PTE_WRITEABLE; in amdgpu_vm_bo_update() 1348 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags); in amdgpu_vm_bo_update() 1354 mapping->last, update_flags, in amdgpu_vm_bo_update()
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| /drivers/md/ |
| A D | dm-cache-metadata.c | 568 static void update_flags(struct cache_disk_superblock *disk_super, in update_flags() function 632 update_flags(disk_super, mutator); in __begin_transaction_flags() 700 update_flags(disk_super, mutator); in __commit_transaction()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 489 union pipe_update_flags update_flags; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 485 if (!pipe_ctx->plane_state->update_flags.bits.full_update) { in dcn201_update_mpcc()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 2973 if (pipe_ctx->plane_state->update_flags.bits.full_update || in dce110_program_front_end_for_pipe() 2974 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || in dce110_program_front_end_for_pipe() 2975 pipe_ctx->plane_state->update_flags.bits.gamma_change) in dce110_program_front_end_for_pipe() 2978 if (pipe_ctx->plane_state->update_flags.bits.full_update) in dce110_program_front_end_for_pipe()
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| /drivers/net/ethernet/mellanox/mlx4/ |
| A D | fw.c | 2409 __be32 update_flags; member 2520 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); in mlx4_config_vxlan_port() 2533 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); in mlx4_disable_rx_port_check() 2546 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); in mlx4_config_roce_v2_port()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 1237 pipe->plane_state->update_flags.bits.full_update = 1; in dcn_validate_bandwidth()
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