| /drivers/gpu/drm/amd/display/dc/sspl/ |
| A D | dc_spl.c | 472 spl_scratch->scl_data.ratios.vert, 19); in spl_calculate_scaling_ratios()
486 spl_scratch->scl_data.ratios.vert); in spl_calculate_scaling_ratios()
698 spl_scratch->scl_data.ratios.vert, in spl_calculate_inits_and_viewports()
765 && data->ratios.vert.value == one in spl_get_dscl_mode()
910 spl_scratch->scl_data.ratios.vert), 8); in spl_get_taps_non_adaptive_scaler()
1314 spl_scratch->scl_data.recip_ratios.vert); in spl_set_easf_data()
1318 spl_scratch->scl_data.recip_ratios.vert); in spl_set_easf_data()
1322 spl_scratch->scl_data.recip_ratios.vert); in spl_set_easf_data()
1326 spl_scratch->scl_data.recip_ratios.vert); in spl_set_easf_data()
1330 spl_scratch->scl_data.recip_ratios.vert); in spl_set_easf_data()
[all …]
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| A D | dc_spl_scl_easf_filters.c | 2368 data->taps.v_taps, data->recip_ratios.vert); in spl_set_filters_data()
2374 data->taps.v_taps, data->ratios.vert); in spl_set_filters_data()
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| A D | dc_spl_types.h | 26 struct spl_fixed31_32 vert; member
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| A D | dcn10_dpp_dscl.c | 137 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
149 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp1_dscl_get_dscl_mode()
288 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
465 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); in dpp1_dscl_find_lb_memory_config()
520 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); in dpp1_dscl_set_manual_ratio_init()
550 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert); in dpp1_dscl_set_manual_ratio_init()
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| A D | dcn10_dpp.c | 133 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
146 if (scl_data->ratios.vert.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
147 scl_data->ratios.vert.value--; in dpp1_get_optimal_number_of_taps()
177 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp1_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| A D | dcn201_dpp.c | 210 if (scl_data->ratios.vert.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
211 scl_data->ratios.vert.value--; in dpp201_get_optimal_number_of_taps()
227 if (dc_fixpt_ceil(scl_data->ratios.vert) > 4) in dpp201_get_optimal_number_of_taps()
254 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp201_get_optimal_number_of_taps()
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| /drivers/media/platform/ti/omap3isp/ |
| A D | ispresizer.c | 319 rgval |= ((ratio->vert - 1) << ISPRSZ_CNT_VRSZ_SHIFT) in resizer_set_ratio()
330 if (ratio->vert > MID_RESIZE_VALUE) in resizer_set_ratio()
807 ratio->vert = ((input->height - 4) * 256 + 255 - 16 - 32 * spv) in resizer_calc_ratios()
809 if (ratio->vert > MID_RESIZE_VALUE) in resizer_calc_ratios()
810 ratio->vert = ((input->height - 7) * 256 + 255 - 32 - 64 * spv) in resizer_calc_ratios()
812 ratio->vert = clamp_t(unsigned int, ratio->vert, in resizer_calc_ratios()
815 if (ratio->vert <= MID_RESIZE_VALUE) { in resizer_calc_ratios()
816 upscaled_height = (output->height - 1) * ratio->vert in resizer_calc_ratios()
820 upscaled_height = (output->height - 1) * ratio->vert in resizer_calc_ratios()
832 if (ratio->vert <= MID_RESIZE_VALUE) { in resizer_calc_ratios()
[all …]
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| A D | ispresizer.h | 61 u32 vert; member
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_transform.c | 288 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
302 data->ratios.vert, in calculate_inits()
320 dc_fixpt_u2d19(data->ratios.vert) << 5; in dce60_calculate_inits()
331 data->ratios.vert, in dce60_calculate_inits()
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
524 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce60_transform_set_scaler()
1195 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
1199 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | transform.h | 128 struct fixed31_32 vert; member
135 int vert; member
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| A D | dcn401_dpp_dscl.c | 139 && data->ratios.vert.value == one in dpp401_dscl_get_dscl_mode()
151 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp401_dscl_get_dscl_mode()
291 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp401_dscl_set_scl_filter()
309 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp401_dscl_set_scl_filter()
481 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); in dpp401_dscl_find_lb_memory_config()
577 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); in dpp401_dscl_set_manual_ratio_init()
607 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert); in dpp401_dscl_set_manual_ratio_init()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| A D | dcn30_dpp.c | 441 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
442 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
472 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); in dpp3_get_optimal_number_of_taps()
485 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) in dpp3_get_optimal_number_of_taps()
486 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); in dpp3_get_optimal_number_of_taps()
509 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp3_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_transform_v.c | 377 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
559 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
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| /drivers/gpu/ipu-v3/ |
| A D | ipu-csi.c | 534 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert) in ipu_csi_set_downsize() argument
544 (vert ? CSI_VERT_DOWNSIZE_EN : 0); in ipu_csi_set_downsize()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_spl_translate.c | 54 ratios->vert = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio >> 5, 3, 19); in populate_ratios_from_splratios()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1151 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1158 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1160 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
1161 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
1166 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1175 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( in calculate_scaling_ratios()
1176 pipe_ctx->plane_res.scl_data.ratios.vert, 19); in calculate_scaling_ratios()
1318 data->ratios.vert, in calculate_inits_and_viewports()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
979 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
984 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 894 scaler_data->ratios.vert.value != dc_fixpt_one.value || in populate_dml21_plane_config_from_plane_state()
925 …plane->composition.scaler_info.plane0.v_ratio = (double)scaler_data->ratios.vert.value / (1ULL << … in populate_dml21_plane_config_from_plane_state()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 1082 scaler_data->ratios.vert.value != dc_fixpt_one.value || in populate_dml_plane_cfg_from_plane_state()
1101 out->VRatio[location] = (dml_float_t)scaler_data->ratios.vert.value / (1ULL << 32); in populate_dml_plane_cfg_from_plane_state()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1673 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); in dcn20_populate_dml_pipes_from_context()
1676 scl->ratios.vert.value != dc_fixpt_one.value in dcn20_populate_dml_pipes_from_context()
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| /drivers/gpu/drm/amd/display/dc/basics/ |
| A D | dce_calcs.c | 2831 …ale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2889 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2934 …ale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); in populate_initial_data()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 3122 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dce110_set_cursor_position()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 1070 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn401_set_cursor_position()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 3618 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn10_set_cursor_position()
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