1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom BCM6345-style Level 1 interrupt controller
8
9maintainers:
10  - Simon Arlott <simon@octiron.net>
11
12description: >
13  This block is a first level interrupt controller that is typically connected
14  directly to one of the HW INT lines on each CPU.
15
16  Key elements of the hardware design include:
17
18    - 32, 64 or 128 incoming level IRQ lines
19
20    - Most onchip peripherals are wired directly to an L1 input
21
22    - A separate instance of the register set for each CPU, allowing individual
23      peripheral IRQs to be routed to any CPU
24
25    - Contains one or more enable/status word pairs per CPU
26
27    - No atomic set/clear operations
28
29    - No polarity/level/edge settings
30
31    - No FIFO or priority encoder logic; software is expected to read all
32      2-4 status words to determine which IRQs are pending
33
34  If multiple reg ranges and interrupt-parent entries are present on an SMP
35  system, the driver will allow IRQ SMP affinity to be set up through the
36  /proc/irq/ interface.  In the simplest possible configuration, only one
37  reg range and one interrupt-parent is needed.
38
39  The driver operates in native CPU endian by default, there is no support for
40  specifying an alternative endianness.
41
42properties:
43  compatible:
44    const: brcm,bcm6345-l1-intc
45
46  reg:
47    description: One entry per CPU core
48    minItems: 1
49    maxItems: 2
50
51  interrupt-controller: true
52
53  "#interrupt-cells":
54    const: 1
55
56  interrupts:
57    description: One entry per CPU core
58    minItems: 1
59    maxItems: 2
60
61required:
62  - compatible
63  - reg
64  - interrupt-controller
65  - '#interrupt-cells'
66  - interrupts
67
68additionalProperties: false
69
70examples:
71  - |
72    interrupt-controller@10000000 {
73        compatible = "brcm,bcm6345-l1-intc";
74        reg = <0x10000020 0x20>,
75              <0x10000040 0x20>;
76
77        interrupt-controller;
78        #interrupt-cells = <1>;
79
80        interrupts = <2>, <3>;
81    };
82