1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell ODMI controller
8
9maintainers:
10  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11
12description:
13  Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
14  be used by on-board peripherals for MSI interrupts.
15
16properties:
17  compatible:
18    const: marvell,odmi-controller
19
20  reg:
21    description: List of register definitions, one for each ODMI frame.
22
23  msi-controller: true
24
25  marvell,odmi-frames:
26    description: Number of ODMI frames available. Each frame provides a number of events.
27    $ref: /schemas/types.yaml#/definitions/uint32
28
29  marvell,spi-base:
30    description: >
31      List of GIC base SPI interrupts, one for each ODMI frame. Those SPI
32      interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96.
33      See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
34      for details.
35    $ref: /schemas/types.yaml#/definitions/uint32-array
36
37required:
38  - compatible
39  - reg
40  - msi-controller
41  - marvell,odmi-frames
42  - marvell,spi-base
43
44additionalProperties: false
45
46examples:
47  - |
48    msi-controller@300000 {
49        compatible = "marvell,odmi-controller";
50        msi-controller;
51        marvell,odmi-frames = <4>;
52        reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>;
53        marvell,spi-base = <128>, <136>, <144>, <152>;
54    };
55