1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ACLINT Supervisor-level Software Interrupt Device
8
9maintainers:
10  - Inochi Amaoto <inochiama@outlook.com>
11
12description:
13  The SSWI device is a part of the ACLINT device. It provides
14  supervisor-level IPI functionality for a set of HARTs on a supported
15  platforms. It provides a register to set an IPI (SETSSIP) for each
16  HART connected to the SSWI device. See draft specification
17  https://github.com/riscvarchive/riscv-aclint
18
19  Following variants of the SSWI ACLINT supported, using dedicated
20  compatible string
21  - THEAD C900
22  - MIPS P8700
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - sophgo,sg2044-aclint-sswi
30          - const: thead,c900-aclint-sswi
31      - items:
32          - const: mips,p8700-aclint-sswi
33
34  reg:
35    maxItems: 1
36
37  "#interrupt-cells":
38    const: 0
39
40  interrupt-controller: true
41
42  interrupts-extended:
43    minItems: 1
44    maxItems: 4095
45
46  riscv,hart-indexes:
47    $ref: /schemas/types.yaml#/definitions/uint32-array
48    minItems: 1
49    maxItems: 4095
50    description:
51      A list of hart indexes that APLIC should use to address each hart
52      that is mentioned in the "interrupts-extended"
53
54additionalProperties: false
55
56required:
57  - compatible
58  - reg
59  - "#interrupt-cells"
60  - interrupt-controller
61  - interrupts-extended
62
63allOf:
64  - if:
65      properties:
66        compatible:
67          contains:
68            const: mips,p8700-aclint-sswi
69    then:
70      required:
71        - riscv,hart-indexes
72    else:
73      properties:
74        riscv,hart-indexes: false
75
76examples:
77  - |
78    //Example 1
79    interrupt-controller@94000000 {
80      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
81      reg = <0x94000000 0x00004000>;
82      #interrupt-cells = <0>;
83      interrupt-controller;
84      interrupts-extended = <&cpu1intc 1>,
85                            <&cpu2intc 1>,
86                            <&cpu3intc 1>,
87                            <&cpu4intc 1>;
88    };
89
90  - |
91    //Example 2
92    interrupt-controller@94000000 {
93      compatible = "mips,p8700-aclint-sswi";
94      reg = <0x94000000 0x00004000>;
95      #interrupt-cells = <0>;
96      interrupt-controller;
97      interrupts-extended = <&cpu1intc 1>,
98                            <&cpu2intc 1>,
99                            <&cpu3intc 1>,
100                            <&cpu4intc 1>;
101      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
102    };
103
104...
105