1.. SPDX-License-Identifier: GPL-2.0 2 3=============================== 4The Linux kernel dpll subsystem 5=============================== 6 7DPLL 8==== 9 10PLL - Phase Locked Loop is an electronic circuit which syntonizes clock 11signal of a device with an external clock signal. Effectively enabling 12device to run on the same clock signal beat as provided on a PLL input. 13 14DPLL - Digital Phase Locked Loop is an integrated circuit which in 15addition to plain PLL behavior incorporates a digital phase detector 16and may have digital divider in the loop. As a result, the frequency on 17DPLL's input and output may be configurable. 18 19Subsystem 20========= 21 22The main purpose of dpll subsystem is to provide general interface 23to configure devices that use any kind of Digital PLL and could use 24different sources of input signal to synchronize to, as well as 25different types of outputs. 26The main interface is NETLINK_GENERIC based protocol with an event 27monitoring multicast group defined. 28 29Device object 30============= 31 32Single dpll device object means single Digital PLL circuit and bunch of 33connected pins. 34It reports the supported modes of operation and current status to the 35user in response to the `do` request of netlink command 36``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem 37with `dump` netlink request of the same command. 38Changing the configuration of dpll device is done with `do` request of 39netlink ``DPLL_CMD_DEVICE_SET`` command. 40A device handle is ``DPLL_A_ID``, it shall be provided to get or set 41configuration of particular device in the system. It can be obtained 42with a ``DPLL_CMD_DEVICE_GET`` `dump` request or 43a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide 44attributes that result in single device match. 45 46Pin object 47========== 48 49A pin is amorphic object which represents either input or output, it 50could be internal component of the device, as well as externally 51connected. 52The number of pins per dpll vary, but usually multiple pins shall be 53provided for a single dpll device. 54Pin's properties, capabilities and status is provided to the user in 55response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. 56It is also possible to list all the pins that were registered in the 57system with `dump` request of ``DPLL_CMD_PIN_GET`` command. 58Configuration of a pin can be changed by `do` request of netlink 59``DPLL_CMD_PIN_SET`` command. 60Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set 61configuration of particular pin in the system. It can be obtained with 62``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` 63request, where user provides attributes that result in single pin match. 64 65Pin selection 66============= 67 68In general, selected pin (the one which signal is driving the dpll 69device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only 70one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll 71device. 72 73Pin selection can be done either manually or automatically, depending 74on hardware capabilities and active dpll device work mode 75(``DPLL_A_MODE`` attribute). The consequence is that there are 76differences for each mode in terms of available pin states, as well as 77for the states the user can request for a dpll device. 78 79In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive 80one of following pin states: 81 82- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device 83- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll 84 device 85 86In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or 87receive one of following pin states: 88 89- ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid 90 input for automatic selection algorithm 91- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as 92 a valid input for automatic selection algorithm 93 94In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive 95pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection 96algorithm locks a dpll device with one of the inputs. 97 98Shared pins 99=========== 100 101A single pin object can be attached to multiple dpll devices. 102Then there are two groups of configuration knobs: 103 1041) Set on a pin - the configuration affects all dpll devices pin is 105 registered to (i.e., ``DPLL_A_PIN_FREQUENCY``), 1062) Set on a pin-dpll tuple - the configuration affects only selected 107 dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, 108 ``DPLL_A_PIN_DIRECTION``). 109 110MUX-type pins 111============= 112 113A pin can be MUX-type, it aggregates child pins and serves as a pin 114multiplexer. One or more pins are registered with MUX-type instead of 115being directly registered to a dpll device. 116Pins registered with a MUX-type pin provide user with additional nested 117attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered 118with. 119If a pin was registered with multiple parent pins, they behave like a 120multiple output multiplexer. In this case output of a 121``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested 122attributes with current state related to each parent, like:: 123 124 'pin': [{{ 125 'clock-id': 282574471561216, 126 'module-name': 'ice', 127 'capabilities': 4, 128 'id': 13, 129 'parent-pin': [ 130 {'parent-id': 2, 'state': 'connected'}, 131 {'parent-id': 3, 'state': 'disconnected'} 132 ], 133 'type': 'synce-eth-port' 134 }}] 135 136Only one child pin can provide its signal to the parent MUX-type pin at 137a time, the selection is done by requesting change of a child pin state 138on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested 139attribute. Example of netlink `set state on parent pin` message format: 140 141 ========================== ============================================= 142 ``DPLL_A_PIN_ID`` child pin id 143 ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration 144 related to parent pin 145 ``DPLL_A_PIN_PARENT_ID`` parent pin id 146 ``DPLL_A_PIN_STATE`` requested pin state on parent 147 ========================== ============================================= 148 149Pin priority 150============ 151 152Some devices might offer a capability of automatic pin selection mode 153(enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). 154Usually, automatic selection is performed on the hardware level, which 155means only pins directly connected to the dpll can be used for automatic 156input pin selection. 157In automatic selection mode, the user cannot manually select a input 158pin for the device, instead the user shall provide all directly 159connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would 160pick a highest priority valid signal and use it to control the DPLL 161device. Example of netlink `set priority on parent pin` message format: 162 163 ============================ ============================================= 164 ``DPLL_A_PIN_ID`` configured pin id 165 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration 166 related to parent dpll device 167 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 168 ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll 169 ============================ ============================================= 170 171Child pin of MUX-type pin is not capable of automatic input pin selection, 172in order to configure active input of a MUX-type pin, the user needs to 173request desired pin state of the child pin on the parent pin, 174as described in the ``MUX-type pins`` chapter. 175 176Phase offset measurement and adjustment 177======================================== 178 179Device may provide ability to measure a phase difference between signals 180on a pin and its parent dpll device. If pin-dpll phase offset measurement 181is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` 182attribute for each parent dpll device. 183 184Device may also provide ability to adjust a signal phase on a pin. 185If pin phase adjustment is supported, minimal and maximal values that pin 186handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond 187with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX`` 188attributes. Configured phase adjust value is provided with 189``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be 190requested with the same attribute with ``DPLL_CMD_PIN_SET`` command. 191 192 =============================== ====================================== 193 ``DPLL_A_PIN_ID`` configured pin id 194 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment 195 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment 196 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 197 adjustment on parent dpll device 198 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting 199 configuration on given parent dpll 200 device 201 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 202 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 203 between a pin and parent dpll device 204 =============================== ====================================== 205 206All phase related values are provided in pico seconds, which represents 207time difference between signals phase. The negative value means that 208phase of signal on pin is earlier in time than dpll's signal. Positive 209value means that phase of signal on pin is later in time than signal of 210a dpll. 211 212Phase adjust (also min and max) values are integers, but measured phase 213offset values are fractional with 3-digit decimal places and shell be 214divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and 215modulo divided to get fractional part. 216 217Phase offset monitor 218==================== 219 220Phase offset measurement is typically performed against the current active 221source. However, some DPLL (Digital Phase-Locked Loop) devices may offer 222the capability to monitor phase offsets across all available inputs. 223The attribute and current feature state shall be included in the response 224message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. 225In such cases, users can also control the feature using the 226``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` 227values for the attribute. 228Once enabled the phase offset measurements for the input shall be returned 229in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. 230 231 =============================== ======================== 232 ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature 233 =============================== ======================== 234 235Embedded SYNC 236============= 237 238Device may provide ability to use Embedded SYNC feature. It allows 239to embed additional SYNC signal into the base frequency of a pin - a one 240special pulse of base frequency signal every time SYNC signal pulse 241happens. The user can configure the frequency of Embedded SYNC. 242The Embedded SYNC capability is always related to a given base frequency 243and HW capabilities. The user is provided a range of Embedded SYNC 244frequencies supported, depending on current base frequency configured for 245the pin. 246 247 ========================================= ================================= 248 ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency 249 ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC 250 frequency ranges 251 ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency 252 ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency 253 ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC 254 ========================================= ================================= 255 256Reference SYNC 257============== 258 259The device may support the Reference SYNC feature, which allows the combination 260of two inputs into a input pair. In this configuration, clock signals 261from both inputs are used to synchronize the DPLL device. The higher frequency 262signal is utilized for the loop bandwidth of the DPLL, while the lower frequency 263signal is used to syntonize the output signal of the DPLL device. This feature 264enables the provision of a high-quality loop bandwidth signal from an external 265source. 266 267A capable input provides a list of inputs that can be bound with to create 268Reference SYNC. To control this feature, the user must request a desired 269state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or 270``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be 271bound to only one other pin at any given time. 272 273 ============================== ========================================== 274 ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or 275 requesting configuration of the Reference 276 SYNC feature 277 ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature 278 ``DPLL_A_PIN_STATE`` state of Reference SYNC connection 279 ============================== ========================================== 280 281Configuration commands group 282============================ 283 284Configuration commands are used to get information about registered 285dpll devices (and pins), as well as set configuration of device or pins. 286As dpll devices must be abstracted and reflect real hardware, 287there is no way to add new dpll device via netlink from user space and 288each device should be registered by its driver. 289 290All netlink commands require ``GENL_ADMIN_PERM``. This is to prevent 291any spamming/DoS from unauthorized userspace applications. 292 293List of netlink commands with possible attributes 294================================================= 295 296Constants identifying command types for dpll device uses a 297``DPLL_CMD_`` prefix and suffix according to command purpose. 298The dpll device related attributes use a ``DPLL_A_`` prefix and 299suffix according to attribute purpose. 300 301 ==================================== ================================= 302 ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID 303 ``DPLL_A_MODULE_NAME`` attr module name of registerer 304 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 305 (EUI-64), as defined by the 306 IEEE 1588 standard 307 ``DPLL_A_TYPE`` attr type of dpll device 308 ==================================== ================================= 309 310 ==================================== ================================= 311 ``DPLL_CMD_DEVICE_GET`` command to get device info or 312 dump list of available devices 313 ``DPLL_A_ID`` attr unique dpll device ID 314 ``DPLL_A_MODULE_NAME`` attr module name of registerer 315 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 316 (EUI-64), as defined by the 317 IEEE 1588 standard 318 ``DPLL_A_MODE`` attr selection mode 319 ``DPLL_A_MODE_SUPPORTED`` attr available selection modes 320 ``DPLL_A_LOCK_STATUS`` attr dpll device lock status 321 ``DPLL_A_TEMP`` attr device temperature info 322 ``DPLL_A_TYPE`` attr type of dpll device 323 ==================================== ================================= 324 325 ==================================== ================================= 326 ``DPLL_CMD_DEVICE_SET`` command to set dpll device config 327 ``DPLL_A_ID`` attr internal dpll device index 328 ``DPLL_A_MODE`` attr selection mode to configure 329 ==================================== ================================= 330 331Constants identifying command types for pins uses a 332``DPLL_CMD_PIN_`` prefix and suffix according to command purpose. 333The pin related attributes use a ``DPLL_A_PIN_`` prefix and suffix 334according to attribute purpose. 335 336 ==================================== ================================= 337 ``DPLL_CMD_PIN_ID_GET`` command to get pin ID 338 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 339 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 340 (EUI-64), as defined by the 341 IEEE 1588 standard 342 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 343 by registerer 344 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 345 by registerer 346 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 347 by registerer 348 ``DPLL_A_PIN_TYPE`` attr type of a pin 349 ==================================== ================================= 350 351 ==================================== ================================== 352 ``DPLL_CMD_PIN_GET`` command to get pin info or dump 353 list of available pins 354 ``DPLL_A_PIN_ID`` attr unique a pin ID 355 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 356 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 357 (EUI-64), as defined by the 358 IEEE 1588 standard 359 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 360 by registerer 361 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 362 by registerer 363 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 364 by registerer 365 ``DPLL_A_PIN_TYPE`` attr type of a pin 366 ``DPLL_A_PIN_FREQUENCY`` attr current frequency of a pin 367 ``DPLL_A_PIN_FREQUENCY_SUPPORTED`` nested attr provides supported 368 frequencies 369 ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency 370 ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency 371 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase 372 adjustment 373 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase 374 adjustment 375 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 376 adjustment on parent device 377 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device 378 the pin is connected with 379 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 380 ``DPLL_A_PIN_PRIO`` attr priority of pin on the 381 dpll device 382 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 383 dpll device 384 ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the 385 parent dpll device 386 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 387 between a pin and parent dpll 388 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 389 the pin is connected with 390 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 391 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 392 pin 393 ``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities 394 ==================================== ================================== 395 396 ==================================== ================================= 397 ``DPLL_CMD_PIN_SET`` command to set pins configuration 398 ``DPLL_A_PIN_ID`` attr unique a pin ID 399 ``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin 400 ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase 401 adjustment on parent device 402 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll 403 device configuration request 404 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 405 ``DPLL_A_PIN_DIRECTION`` attr requested direction of a pin 406 ``DPLL_A_PIN_PRIO`` attr requested priority of pin on 407 the dpll device 408 ``DPLL_A_PIN_STATE`` attr requested state of pin on 409 the dpll device 410 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 411 configuration request 412 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 413 ``DPLL_A_PIN_STATE`` attr requested state of pin on 414 parent pin 415 ==================================== ================================= 416 417Netlink dump requests 418===================== 419 420The ``DPLL_CMD_DEVICE_GET`` and ``DPLL_CMD_PIN_GET`` commands are 421capable of dump type netlink requests, in which case the response is in 422the same format as for their ``do`` request, but every device or pin 423registered in the system is returned. 424 425SET commands format 426=================== 427 428``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides 429``DPLL_A_ID``, which is unique identifier of dpll device in the system, 430as well as parameter being configured (``DPLL_A_MODE``). 431 432``DPLL_CMD_PIN_SET`` - to target a pin user must provide a 433``DPLL_A_PIN_ID``, which is unique identifier of a pin in the system. 434Also configured pin parameters must be added. 435If ``DPLL_A_PIN_FREQUENCY`` is configured, this affects all the dpll 436devices that are connected with the pin, that is why frequency attribute 437shall not be enclosed in ``DPLL_A_PIN_PARENT_DEVICE``. 438Other attributes: ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE`` or 439``DPLL_A_PIN_DIRECTION`` must be enclosed in 440``DPLL_A_PIN_PARENT_DEVICE`` as their configuration relates to only one 441of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is 442also required inside that nest. 443For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in 444similar way, by enclosing required state in ``DPLL_A_PIN_PARENT_PIN`` 445nested attribute and targeted parent pin id in ``DPLL_A_PIN_PARENT_ID``. 446 447In general, it is possible to configure multiple parameters at once, but 448internally each parameter change will be invoked separately, where order 449of configuration is not guaranteed by any means. 450 451Configuration pre-defined enums 452=============================== 453 454.. kernel-doc:: include/uapi/linux/dpll.h 455 456Notifications 457============= 458 459dpll device can provide notifications regarding status changes of the 460device, i.e. lock status changes, input/output changes or other alarms. 461There is one multicast group that is used to notify user-space apps via 462netlink socket: ``DPLL_MCGRP_MONITOR`` 463 464Notifications messages: 465 466 ============================== ===================================== 467 ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created 468 ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted 469 ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed 470 ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created 471 ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted 472 ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed 473 ============================== ===================================== 474 475Events format is the same as for the corresponding get command. 476Format of ``DPLL_CMD_DEVICE_`` events is the same as response of 477``DPLL_CMD_DEVICE_GET``. 478Format of ``DPLL_CMD_PIN_`` events is same as response of 479``DPLL_CMD_PIN_GET``. 480 481Device driver implementation 482============================ 483 484Device is allocated by dpll_device_get() call. Second call with the 485same arguments will not create new object but provides pointer to 486previously created device for given arguments, it also increases 487refcount of that object. 488Device is deallocated by dpll_device_put() call, which first 489decreases the refcount, once refcount is cleared the object is 490destroyed. 491 492Device should implement set of operations and register device via 493dpll_device_register() at which point it becomes available to the 494users. Multiple driver instances can obtain reference to it with 495dpll_device_get(), as well as register dpll device with their own 496ops and priv. 497 498The pins are allocated separately with dpll_pin_get(), it works 499similarly to dpll_device_get(). Function first creates object and then 500for each call with the same arguments only the object refcount 501increases. Also dpll_pin_put() works similarly to dpll_device_put(). 502 503A pin can be registered with parent dpll device or parent pin, depending 504on hardware needs. Each registration requires registerer to provide set 505of pin callbacks, and private data pointer for calling them: 506 507- dpll_pin_register() - register pin with a dpll device, 508- dpll_pin_on_pin_register() - register pin with another MUX type pin. 509 510Notifications of adding or removing dpll devices are created within 511subsystem itself. 512Notifications about registering/deregistering pins are also invoked by 513the subsystem. 514Notifications about status changes either of dpll device or a pin are 515invoked in two ways: 516 517- after successful change was requested on dpll subsystem, the subsystem 518 calls corresponding notification, 519- requested by device driver with dpll_device_change_ntf() or 520 dpll_pin_change_ntf() when driver informs about the status change. 521 522The device driver using dpll interface is not required to implement all 523the callback operation. Nevertheless, there are few required to be 524implemented. 525Required dpll device level callback operations: 526 527- ``.mode_get``, 528- ``.lock_status_get``. 529 530Required pin level callback operations: 531 532- ``.state_on_dpll_get`` (pins registered with dpll device), 533- ``.state_on_pin_get`` (pins registered with parent pin), 534- ``.direction_get``. 535 536Every other operation handler is checked for existence and 537``-EOPNOTSUPP`` is returned in case of absence of specific handler. 538 539The simplest implementation is in the OCP TimeCard driver. The ops 540structures are defined like this: 541 542.. code-block:: c 543 544 static const struct dpll_device_ops dpll_ops = { 545 .lock_status_get = ptp_ocp_dpll_lock_status_get, 546 .mode_get = ptp_ocp_dpll_mode_get, 547 .mode_supported = ptp_ocp_dpll_mode_supported, 548 }; 549 550 static const struct dpll_pin_ops dpll_pins_ops = { 551 .frequency_get = ptp_ocp_dpll_frequency_get, 552 .frequency_set = ptp_ocp_dpll_frequency_set, 553 .direction_get = ptp_ocp_dpll_direction_get, 554 .direction_set = ptp_ocp_dpll_direction_set, 555 .state_on_dpll_get = ptp_ocp_dpll_state_get, 556 }; 557 558The registration part is then looks like this part: 559 560.. code-block:: c 561 562 clkid = pci_get_dsn(pdev); 563 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); 564 if (IS_ERR(bp->dpll)) { 565 err = PTR_ERR(bp->dpll); 566 dev_err(&pdev->dev, "dpll_device_alloc failed\n"); 567 goto out; 568 } 569 570 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); 571 if (err) 572 goto out; 573 574 for (i = 0; i < OCP_SMA_NUM; i++) { 575 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); 576 if (IS_ERR(bp->sma[i].dpll_pin)) { 577 err = PTR_ERR(bp->dpll); 578 goto out_dpll; 579 } 580 581 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, 582 &bp->sma[i]); 583 if (err) { 584 dpll_pin_put(bp->sma[i].dpll_pin); 585 goto out_dpll; 586 } 587 } 588 589In the error path we have to rewind every allocation in the reverse order: 590 591.. code-block:: c 592 593 while (i) { 594 --i; 595 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 596 dpll_pin_put(bp->sma[i].dpll_pin); 597 } 598 dpll_device_put(bp->dpll); 599 600More complex example can be found in Intel's ICE driver or nVidia's mlx5 driver. 601 602SyncE enablement 603================ 604For SyncE enablement it is required to allow control over dpll device 605for a software application which monitors and configures the inputs of 606dpll device in response to current state of a dpll device and its 607inputs. 608In such scenario, dpll device input signal shall be also configurable 609to drive dpll with signal recovered from the PHY netdevice. 610This is done by exposing a pin to the netdevice - attaching pin to the 611netdevice itself with 612``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. 613Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user 614as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in 615nested attribute ``IFLA_DPLL_PIN``. 616