1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Hyper-V specific APIC code.
5 *
6 * Copyright (C) 2018, Microsoft, Inc.
7 *
8 * Author : K. Y. Srinivasan <kys@microsoft.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 */
21
22 #include <linux/types.h>
23 #include <linux/vmalloc.h>
24 #include <linux/mm.h>
25 #include <linux/clockchips.h>
26 #include <linux/slab.h>
27 #include <linux/cpuhotplug.h>
28 #include <asm/hypervisor.h>
29 #include <asm/mshyperv.h>
30 #include <asm/apic.h>
31 #include <asm/msr.h>
32
33 #include <asm/trace/hyperv.h>
34
35 static struct apic orig_apic;
36
hv_apic_icr_read(void)37 static u64 hv_apic_icr_read(void)
38 {
39 u64 reg_val;
40
41 rdmsrq(HV_X64_MSR_ICR, reg_val);
42 return reg_val;
43 }
44
hv_apic_icr_write(u32 low,u32 id)45 static void hv_apic_icr_write(u32 low, u32 id)
46 {
47 u64 reg_val;
48
49 reg_val = SET_XAPIC_DEST_FIELD(id);
50 reg_val = reg_val << 32;
51 reg_val |= low;
52
53 wrmsrq(HV_X64_MSR_ICR, reg_val);
54 }
55
hv_apic_read(u32 reg)56 static u32 hv_apic_read(u32 reg)
57 {
58 u32 reg_val, hi;
59
60 switch (reg) {
61 case APIC_EOI:
62 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
63 (void)hi;
64 return reg_val;
65 case APIC_TASKPRI:
66 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
67 (void)hi;
68 return reg_val;
69
70 default:
71 return native_apic_mem_read(reg);
72 }
73 }
74
hv_apic_write(u32 reg,u32 val)75 static void hv_apic_write(u32 reg, u32 val)
76 {
77 switch (reg) {
78 case APIC_EOI:
79 wrmsrq(HV_X64_MSR_EOI, val);
80 break;
81 case APIC_TASKPRI:
82 wrmsrq(HV_X64_MSR_TPR, val);
83 break;
84 default:
85 native_apic_mem_write(reg, val);
86 }
87 }
88
hv_apic_eoi_write(void)89 static void hv_apic_eoi_write(void)
90 {
91 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
92
93 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
94 return;
95
96 wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK);
97 }
98
cpu_is_self(int cpu)99 static bool cpu_is_self(int cpu)
100 {
101 return cpu == smp_processor_id();
102 }
103
104 /*
105 * IPI implementation on Hyper-V.
106 */
__send_ipi_mask_ex(const struct cpumask * mask,int vector,bool exclude_self)107 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
108 bool exclude_self)
109 {
110 struct hv_send_ipi_ex *ipi_arg;
111 unsigned long flags;
112 int nr_bank = 0;
113 u64 status = HV_STATUS_INVALID_PARAMETER;
114
115 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
116 return false;
117
118 local_irq_save(flags);
119 ipi_arg = *this_cpu_ptr(hyperv_pcpu_input_arg);
120
121 if (unlikely(!ipi_arg))
122 goto ipi_mask_ex_done;
123
124 ipi_arg->vector = vector;
125 ipi_arg->reserved = 0;
126 ipi_arg->vp_set.valid_bank_mask = 0;
127
128 /*
129 * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET
130 * when the IPI is sent to all currently present CPUs.
131 */
132 if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) {
133 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
134
135 nr_bank = cpumask_to_vpset_skip(&ipi_arg->vp_set, mask,
136 exclude_self ? cpu_is_self : NULL);
137
138 /*
139 * 'nr_bank <= 0' means some CPUs in cpumask can't be
140 * represented in VP_SET. Return an error and fall back to
141 * native (architectural) method of sending IPIs.
142 */
143 if (nr_bank <= 0)
144 goto ipi_mask_ex_done;
145 } else {
146 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
147 }
148
149 /*
150 * For this hypercall, Hyper-V treats the valid_bank_mask field
151 * of ipi_arg->vp_set as part of the fixed size input header.
152 * So the variable input header size is equal to nr_bank.
153 */
154 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
155 ipi_arg, NULL);
156
157 ipi_mask_ex_done:
158 local_irq_restore(flags);
159 return hv_result_success(status);
160 }
161
__send_ipi_mask(const struct cpumask * mask,int vector,bool exclude_self)162 static bool __send_ipi_mask(const struct cpumask *mask, int vector,
163 bool exclude_self)
164 {
165 int cur_cpu, vcpu, this_cpu = smp_processor_id();
166 struct hv_send_ipi ipi_arg;
167 u64 status;
168 unsigned int weight;
169
170 trace_hyperv_send_ipi_mask(mask, vector);
171
172 weight = cpumask_weight(mask);
173
174 /*
175 * Do nothing if
176 * 1. the mask is empty
177 * 2. the mask only contains self when exclude_self is true
178 */
179 if (weight == 0 ||
180 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
181 return true;
182
183 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
184 if (!hv_hypercall_pg) {
185 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
186 return false;
187 }
188
189 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
190 return false;
191
192 /*
193 * From the supplied CPU set we need to figure out if we can get away
194 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
195 * highest VP number in the set is < 64. As VP numbers are usually in
196 * ascending order and match Linux CPU ids, here is an optimization:
197 * we check the VP number for the highest bit in the supplied set first
198 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
199 * a must. We will also check all VP numbers when walking the supplied
200 * CPU set to remain correct in all cases.
201 */
202 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
203 goto do_ex_hypercall;
204
205 ipi_arg.vector = vector;
206 ipi_arg.cpu_mask = 0;
207
208 for_each_cpu(cur_cpu, mask) {
209 if (exclude_self && cur_cpu == this_cpu)
210 continue;
211 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
212 if (vcpu == VP_INVAL)
213 return false;
214
215 /*
216 * This particular version of the IPI hypercall can
217 * only target up to 64 CPUs.
218 */
219 if (vcpu >= 64)
220 goto do_ex_hypercall;
221
222 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
223 }
224
225 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
226 ipi_arg.cpu_mask);
227 return hv_result_success(status);
228
229 do_ex_hypercall:
230 return __send_ipi_mask_ex(mask, vector, exclude_self);
231 }
232
__send_ipi_one(int cpu,int vector)233 static bool __send_ipi_one(int cpu, int vector)
234 {
235 int vp = hv_cpu_number_to_vp_number(cpu);
236 u64 status;
237
238 trace_hyperv_send_ipi_one(cpu, vector);
239
240 if (vp == VP_INVAL)
241 return false;
242
243 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
244 if (!hv_hypercall_pg) {
245 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
246 return false;
247 }
248
249 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
250 return false;
251
252 if (vp >= 64)
253 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
254
255 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
256 return hv_result_success(status);
257 }
258
hv_send_ipi(int cpu,int vector)259 static void hv_send_ipi(int cpu, int vector)
260 {
261 if (!__send_ipi_one(cpu, vector))
262 orig_apic.send_IPI(cpu, vector);
263 }
264
hv_send_ipi_mask(const struct cpumask * mask,int vector)265 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
266 {
267 if (!__send_ipi_mask(mask, vector, false))
268 orig_apic.send_IPI_mask(mask, vector);
269 }
270
hv_send_ipi_mask_allbutself(const struct cpumask * mask,int vector)271 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
272 {
273 if (!__send_ipi_mask(mask, vector, true))
274 orig_apic.send_IPI_mask_allbutself(mask, vector);
275 }
276
hv_send_ipi_allbutself(int vector)277 static void hv_send_ipi_allbutself(int vector)
278 {
279 hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
280 }
281
hv_send_ipi_all(int vector)282 static void hv_send_ipi_all(int vector)
283 {
284 if (!__send_ipi_mask(cpu_online_mask, vector, false))
285 orig_apic.send_IPI_all(vector);
286 }
287
hv_send_ipi_self(int vector)288 static void hv_send_ipi_self(int vector)
289 {
290 if (!__send_ipi_one(smp_processor_id(), vector))
291 orig_apic.send_IPI_self(vector);
292 }
293
hv_apic_init(void)294 void __init hv_apic_init(void)
295 {
296 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
297 pr_info("Hyper-V: Using IPI hypercalls\n");
298 /*
299 * Set the IPI entry points.
300 */
301 orig_apic = *apic;
302
303 apic_update_callback(send_IPI, hv_send_ipi);
304 apic_update_callback(send_IPI_mask, hv_send_ipi_mask);
305 apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself);
306 apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself);
307 apic_update_callback(send_IPI_all, hv_send_ipi_all);
308 apic_update_callback(send_IPI_self, hv_send_ipi_self);
309 }
310
311 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
312 pr_info("Hyper-V: Using enlightened APIC (%s mode)",
313 x2apic_enabled() ? "x2apic" : "xapic");
314 /*
315 * When in x2apic mode, don't use the Hyper-V specific APIC
316 * accessors since the field layout in the ICR register is
317 * different in x2apic mode. Furthermore, the architectural
318 * x2apic MSRs function just as well as the Hyper-V
319 * synthetic APIC MSRs, so there's no benefit in having
320 * separate Hyper-V accessors for x2apic mode. The only
321 * exception is hv_apic_eoi_write, because it benefits from
322 * lazy EOI when available, but the same accessor works for
323 * both xapic and x2apic because the field layout is the same.
324 */
325 apic_update_callback(eoi, hv_apic_eoi_write);
326 if (!x2apic_enabled()) {
327 apic_update_callback(read, hv_apic_read);
328 apic_update_callback(write, hv_apic_write);
329 apic_update_callback(icr_write, hv_apic_icr_write);
330 apic_update_callback(icr_read, hv_apic_icr_read);
331 }
332 }
333 }
334