1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
4 */
5
6 #include <linux/cpufreq.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
14
15 #define TEGRA186_NUM_CLUSTERS 2
16 #define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4))
17 #define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4))
18 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
19 #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
20 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
21
22 struct tegra186_cpufreq_cpu {
23 unsigned int bpmp_cluster_id;
24 unsigned int edvd_offset;
25 };
26
27 static const struct tegra186_cpufreq_cpu tegra186_cpus[] = {
28 /* CPU0 - A57 Cluster */
29 {
30 .bpmp_cluster_id = 1,
31 .edvd_offset = EDVD_OFFSET_A57(0)
32 },
33 /* CPU1 - Denver Cluster */
34 {
35 .bpmp_cluster_id = 0,
36 .edvd_offset = EDVD_OFFSET_DENVER(0)
37 },
38 /* CPU2 - Denver Cluster */
39 {
40 .bpmp_cluster_id = 0,
41 .edvd_offset = EDVD_OFFSET_DENVER(1)
42 },
43 /* CPU3 - A57 Cluster */
44 {
45 .bpmp_cluster_id = 1,
46 .edvd_offset = EDVD_OFFSET_A57(1)
47 },
48 /* CPU4 - A57 Cluster */
49 {
50 .bpmp_cluster_id = 1,
51 .edvd_offset = EDVD_OFFSET_A57(2)
52 },
53 /* CPU5 - A57 Cluster */
54 {
55 .bpmp_cluster_id = 1,
56 .edvd_offset = EDVD_OFFSET_A57(3)
57 },
58 };
59
60 struct tegra186_cpufreq_cluster {
61 struct cpufreq_frequency_table *table;
62 u32 ref_clk_khz;
63 u32 div;
64 };
65
66 struct tegra186_cpufreq_data {
67 void __iomem *regs;
68 const struct tegra186_cpufreq_cpu *cpus;
69 struct tegra186_cpufreq_cluster clusters[];
70 };
71
tegra186_cpufreq_init(struct cpufreq_policy * policy)72 static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
73 {
74 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
75 unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;
76 u32 cpu;
77
78 policy->freq_table = data->clusters[cluster].table;
79 policy->cpuinfo.transition_latency = 300 * 1000;
80 policy->driver_data = NULL;
81
82 /* set same policy for all cpus in a cluster */
83 for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) {
84 if (data->cpus[cpu].bpmp_cluster_id == cluster)
85 cpumask_set_cpu(cpu, policy->cpus);
86 }
87
88 return 0;
89 }
90
tegra186_cpufreq_set_target(struct cpufreq_policy * policy,unsigned int index)91 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
92 unsigned int index)
93 {
94 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
95 struct cpufreq_frequency_table *tbl = policy->freq_table + index;
96 unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset;
97 u32 edvd_val = tbl->driver_data;
98
99 writel(edvd_val, data->regs + edvd_offset);
100
101 return 0;
102 }
103
tegra186_cpufreq_get(unsigned int cpu)104 static unsigned int tegra186_cpufreq_get(unsigned int cpu)
105 {
106 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
107 struct tegra186_cpufreq_cluster *cluster;
108 struct cpufreq_policy *policy;
109 unsigned int edvd_offset, cluster_id;
110 u32 ndiv;
111
112 policy = cpufreq_cpu_get(cpu);
113 if (!policy)
114 return 0;
115
116 edvd_offset = data->cpus[policy->cpu].edvd_offset;
117 ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK;
118 cluster_id = data->cpus[policy->cpu].bpmp_cluster_id;
119 cluster = &data->clusters[cluster_id];
120 cpufreq_cpu_put(policy);
121
122 return (cluster->ref_clk_khz * ndiv) / cluster->div;
123 }
124
125 static struct cpufreq_driver tegra186_cpufreq_driver = {
126 .name = "tegra186",
127 .flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
128 CPUFREQ_NEED_INITIAL_FREQ_CHECK,
129 .get = tegra186_cpufreq_get,
130 .verify = cpufreq_generic_frequency_table_verify,
131 .target_index = tegra186_cpufreq_set_target,
132 .init = tegra186_cpufreq_init,
133 };
134
init_vhint_table(struct platform_device * pdev,struct tegra_bpmp * bpmp,struct tegra186_cpufreq_cluster * cluster,unsigned int cluster_id)135 static struct cpufreq_frequency_table *init_vhint_table(
136 struct platform_device *pdev, struct tegra_bpmp *bpmp,
137 struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id)
138 {
139 struct cpufreq_frequency_table *table;
140 struct mrq_cpu_vhint_request req;
141 struct tegra_bpmp_message msg;
142 struct cpu_vhint_data *data;
143 int err, i, j, num_rates = 0;
144 dma_addr_t phys;
145 void *virt;
146
147 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
148 GFP_KERNEL);
149 if (!virt)
150 return ERR_PTR(-ENOMEM);
151
152 data = (struct cpu_vhint_data *)virt;
153
154 memset(&req, 0, sizeof(req));
155 req.addr = phys;
156 req.cluster_id = cluster_id;
157
158 memset(&msg, 0, sizeof(msg));
159 msg.mrq = MRQ_CPU_VHINT;
160 msg.tx.data = &req;
161 msg.tx.size = sizeof(req);
162
163 err = tegra_bpmp_transfer(bpmp, &msg);
164 if (err) {
165 table = ERR_PTR(err);
166 goto free;
167 }
168 if (msg.rx.ret) {
169 table = ERR_PTR(-EINVAL);
170 goto free;
171 }
172
173 for (i = data->vfloor; i <= data->vceil; i++) {
174 u16 ndiv = data->ndiv[i];
175
176 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
177 continue;
178
179 /* Only store lowest voltage index for each rate */
180 if (i > 0 && ndiv == data->ndiv[i - 1])
181 continue;
182
183 num_rates++;
184 }
185
186 table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
187 GFP_KERNEL);
188 if (!table) {
189 table = ERR_PTR(-ENOMEM);
190 goto free;
191 }
192
193 cluster->ref_clk_khz = data->ref_clk_hz / 1000;
194 cluster->div = data->pdiv * data->mdiv;
195
196 for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
197 struct cpufreq_frequency_table *point;
198 u16 ndiv = data->ndiv[i];
199 u32 edvd_val = 0;
200
201 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
202 continue;
203
204 /* Only store lowest voltage index for each rate */
205 if (i > 0 && ndiv == data->ndiv[i - 1])
206 continue;
207
208 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
209 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
210
211 point = &table[j++];
212 point->driver_data = edvd_val;
213 point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
214 }
215
216 table[j].frequency = CPUFREQ_TABLE_END;
217
218 free:
219 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
220
221 return table;
222 }
223
tegra186_cpufreq_probe(struct platform_device * pdev)224 static int tegra186_cpufreq_probe(struct platform_device *pdev)
225 {
226 struct tegra186_cpufreq_data *data;
227 struct tegra_bpmp *bpmp;
228 unsigned int i = 0, err;
229
230 data = devm_kzalloc(&pdev->dev,
231 struct_size(data, clusters, TEGRA186_NUM_CLUSTERS),
232 GFP_KERNEL);
233 if (!data)
234 return -ENOMEM;
235
236 data->cpus = tegra186_cpus;
237
238 bpmp = tegra_bpmp_get(&pdev->dev);
239 if (IS_ERR(bpmp))
240 return PTR_ERR(bpmp);
241
242 data->regs = devm_platform_ioremap_resource(pdev, 0);
243 if (IS_ERR(data->regs)) {
244 err = PTR_ERR(data->regs);
245 goto put_bpmp;
246 }
247
248 for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) {
249 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
250
251 cluster->table = init_vhint_table(pdev, bpmp, cluster, i);
252 if (IS_ERR(cluster->table)) {
253 err = PTR_ERR(cluster->table);
254 goto put_bpmp;
255 }
256 }
257
258 tegra186_cpufreq_driver.driver_data = data;
259
260 err = cpufreq_register_driver(&tegra186_cpufreq_driver);
261
262 put_bpmp:
263 tegra_bpmp_put(bpmp);
264
265 return err;
266 }
267
tegra186_cpufreq_remove(struct platform_device * pdev)268 static void tegra186_cpufreq_remove(struct platform_device *pdev)
269 {
270 cpufreq_unregister_driver(&tegra186_cpufreq_driver);
271 }
272
273 static const struct of_device_id tegra186_cpufreq_of_match[] = {
274 { .compatible = "nvidia,tegra186-ccplex-cluster", },
275 { }
276 };
277 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
278
279 static struct platform_driver tegra186_cpufreq_platform_driver = {
280 .driver = {
281 .name = "tegra186-cpufreq",
282 .of_match_table = tegra186_cpufreq_of_match,
283 },
284 .probe = tegra186_cpufreq_probe,
285 .remove = tegra186_cpufreq_remove,
286 };
287 module_platform_driver(tegra186_cpufreq_platform_driver);
288
289 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
290 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
291 MODULE_LICENSE("GPL v2");
292