1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "aldebaran.h"
25 #include "amdgpu_reset.h"
26 #include "amdgpu_amdkfd.h"
27 #include "amdgpu_dpm.h"
28 #include "amdgpu_job.h"
29 #include "amdgpu_ring.h"
30 #include "amdgpu_ras.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_xgmi.h"
33
aldebaran_is_mode2_default(struct amdgpu_reset_control * reset_ctl)34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35 {
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
37
38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
39 adev->gmc.xgmi.connected_to_cpu))
40 return true;
41
42 return false;
43 }
44
45 static struct amdgpu_reset_handler *
aldebaran_get_reset_handler(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
47 struct amdgpu_reset_context *reset_context)
48 {
49 struct amdgpu_reset_handler *handler;
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
51 int i;
52
53 if (reset_context->method == AMD_RESET_METHOD_NONE) {
54 if (aldebaran_is_mode2_default(reset_ctl))
55 reset_context->method = AMD_RESET_METHOD_MODE2;
56 else
57 reset_context->method = amdgpu_asic_reset_method(adev);
58 }
59
60 if (reset_context->method != AMD_RESET_METHOD_NONE) {
61 dev_dbg(adev->dev, "Getting reset handler for method %d\n",
62 reset_context->method);
63 for_each_handler(i, handler, reset_ctl) {
64 if (handler->reset_method == reset_context->method)
65 return handler;
66 }
67 }
68
69 dev_dbg(adev->dev, "Reset handler not found!\n");
70
71 return NULL;
72 }
73
aldebaran_get_ip_block_mask(struct amdgpu_device * adev)74 static inline uint32_t aldebaran_get_ip_block_mask(struct amdgpu_device *adev)
75 {
76 uint32_t ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) |
77 BIT(AMD_IP_BLOCK_TYPE_SDMA);
78
79 if (adev->aid_mask)
80 ip_block_mask |= BIT(AMD_IP_BLOCK_TYPE_IH);
81
82 return ip_block_mask;
83 }
84
aldebaran_mode2_suspend_ip(struct amdgpu_device * adev)85 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
86 {
87 uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);
88 uint32_t ip_block;
89 int r, i;
90
91 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
92 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
93
94 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
95 ip_block = BIT(adev->ip_blocks[i].version->type);
96 if (!(ip_block_mask & ip_block))
97 continue;
98
99 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
100 if (r)
101 return r;
102 }
103
104 return 0;
105 }
106
107 static int
aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)108 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
109 struct amdgpu_reset_context *reset_context)
110 {
111 int r = 0;
112 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
113
114 dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
115 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
116 if (!amdgpu_sriov_vf(adev))
117 r = aldebaran_mode2_suspend_ip(adev);
118
119 return r;
120 }
121
aldebaran_async_reset(struct work_struct * work)122 static void aldebaran_async_reset(struct work_struct *work)
123 {
124 struct amdgpu_reset_handler *handler;
125 struct amdgpu_reset_control *reset_ctl =
126 container_of(work, struct amdgpu_reset_control, reset_work);
127 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
128 int i;
129
130 for_each_handler(i, handler, reset_ctl) {
131 if (handler->reset_method == reset_ctl->active_reset) {
132 dev_dbg(adev->dev, "Resetting device\n");
133 handler->do_reset(adev);
134 break;
135 }
136 }
137 }
138
aldebaran_mode2_reset(struct amdgpu_device * adev)139 static int aldebaran_mode2_reset(struct amdgpu_device *adev)
140 {
141 /* disable BM */
142 pci_clear_master(adev->pdev);
143 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
144 return adev->asic_reset_res;
145 }
146
147 static int
aldebaran_mode2_perform_reset(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)148 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
149 struct amdgpu_reset_context *reset_context)
150 {
151 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
152 struct list_head *reset_device_list = reset_context->reset_device_list;
153 struct amdgpu_device *tmp_adev = NULL;
154 int r = 0;
155
156 dev_dbg(adev->dev, "aldebaran perform hw reset\n");
157
158 if (reset_device_list == NULL)
159 return -EINVAL;
160
161 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
162 reset_context->hive == NULL) {
163 /* Wrong context, return error */
164 return -EINVAL;
165 }
166
167 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
168 mutex_lock(&tmp_adev->reset_cntl->reset_lock);
169 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
170 }
171 /*
172 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
173 * them together so that they can be completed asynchronously on multiple nodes
174 */
175 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
176 /* For XGMI run all resets in parallel to speed up the process */
177 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
178 if (!queue_work(system_unbound_wq,
179 &tmp_adev->reset_cntl->reset_work))
180 r = -EALREADY;
181 } else
182 r = aldebaran_mode2_reset(tmp_adev);
183 if (r) {
184 dev_err(tmp_adev->dev,
185 "ASIC reset failed with error, %d for drm dev, %s",
186 r, adev_to_drm(tmp_adev)->unique);
187 break;
188 }
189 }
190
191 /* For XGMI wait for all resets to complete before proceed */
192 if (!r) {
193 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
194 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
195 flush_work(&tmp_adev->reset_cntl->reset_work);
196 r = tmp_adev->asic_reset_res;
197 if (r)
198 break;
199 }
200 }
201 }
202
203 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
204 mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
205 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
206 }
207
208 return r;
209 }
210
aldebaran_mode2_restore_ip(struct amdgpu_device * adev)211 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
212 {
213 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
214 uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);
215 struct amdgpu_firmware_info *ucode;
216 struct amdgpu_ip_block *cmn_block;
217 struct amdgpu_ip_block *ih_block;
218 int ucode_count = 0;
219 int i, r;
220
221 dev_dbg(adev->dev, "Reloading ucodes after reset\n");
222 for (i = 0; i < adev->firmware.max_ucodes; i++) {
223 ucode = &adev->firmware.ucode[i];
224 if (!ucode->fw)
225 continue;
226 switch (ucode->ucode_id) {
227 case AMDGPU_UCODE_ID_SDMA0:
228 case AMDGPU_UCODE_ID_SDMA1:
229 case AMDGPU_UCODE_ID_SDMA2:
230 case AMDGPU_UCODE_ID_SDMA3:
231 case AMDGPU_UCODE_ID_SDMA4:
232 case AMDGPU_UCODE_ID_SDMA5:
233 case AMDGPU_UCODE_ID_SDMA6:
234 case AMDGPU_UCODE_ID_SDMA7:
235 case AMDGPU_UCODE_ID_CP_MEC1:
236 case AMDGPU_UCODE_ID_CP_MEC1_JT:
237 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
238 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
239 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
240 case AMDGPU_UCODE_ID_RLC_G:
241 ucode_list[ucode_count++] = ucode;
242 break;
243 default:
244 break;
245 }
246 }
247
248 /* Reinit NBIF block */
249 cmn_block =
250 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
251 if (unlikely(!cmn_block)) {
252 dev_err(adev->dev, "Failed to get BIF handle\n");
253 return -EINVAL;
254 }
255 r = amdgpu_ip_block_resume(cmn_block);
256 if (r)
257 return r;
258
259 if (ip_block_mask & BIT(AMD_IP_BLOCK_TYPE_IH)) {
260 ih_block = amdgpu_device_ip_get_ip_block(adev,
261 AMD_IP_BLOCK_TYPE_IH);
262 if (unlikely(!ih_block)) {
263 dev_err(adev->dev, "Failed to get IH handle\n");
264 return -EINVAL;
265 }
266 r = amdgpu_ip_block_resume(ih_block);
267 if (r)
268 return r;
269 }
270
271 /* Reinit GFXHUB */
272 adev->gfxhub.funcs->init(adev);
273 r = adev->gfxhub.funcs->gart_enable(adev);
274 if (r) {
275 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
276 return r;
277 }
278
279 /* Reload GFX firmware */
280 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
281 if (r) {
282 dev_err(adev->dev, "GFX ucode load failed after reset\n");
283 return r;
284 }
285
286 /* Resume RLC, FW needs RLC alive to complete reset process */
287 adev->gfx.rlc.funcs->resume(adev);
288
289 /* Wait for FW reset event complete */
290 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
291 if (r) {
292 dev_err(adev->dev,
293 "Failed to get response from firmware after reset\n");
294 return r;
295 }
296
297 for (i = 0; i < adev->num_ip_blocks; i++) {
298 if (!(adev->ip_blocks[i].version->type ==
299 AMD_IP_BLOCK_TYPE_GFX ||
300 adev->ip_blocks[i].version->type ==
301 AMD_IP_BLOCK_TYPE_SDMA))
302 continue;
303
304 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
305 if (r)
306 return r;
307 }
308
309 for (i = 0; i < adev->num_ip_blocks; i++) {
310 if (!(adev->ip_blocks[i].version->type ==
311 AMD_IP_BLOCK_TYPE_GFX ||
312 adev->ip_blocks[i].version->type ==
313 AMD_IP_BLOCK_TYPE_SDMA ||
314 adev->ip_blocks[i].version->type ==
315 AMD_IP_BLOCK_TYPE_COMMON))
316 continue;
317
318 if (adev->ip_blocks[i].version->funcs->late_init) {
319 r = adev->ip_blocks[i].version->funcs->late_init(
320 &adev->ip_blocks[i]);
321 if (r) {
322 dev_err(adev->dev,
323 "late_init of IP block <%s> failed %d after reset\n",
324 adev->ip_blocks[i].version->funcs->name,
325 r);
326 return r;
327 }
328 }
329 adev->ip_blocks[i].status.late_initialized = true;
330 }
331
332 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
333 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
334
335 return r;
336 }
337
338 static int
aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)339 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
340 struct amdgpu_reset_context *reset_context)
341 {
342 struct list_head *reset_device_list = reset_context->reset_device_list;
343 struct amdgpu_device *tmp_adev = NULL;
344 struct amdgpu_ras *con;
345 int r;
346
347 if (reset_device_list == NULL)
348 return -EINVAL;
349
350 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) ==
351 IP_VERSION(13, 0, 2) &&
352 reset_context->hive == NULL) {
353 /* Wrong context, return error */
354 return -EINVAL;
355 }
356
357 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
358 amdgpu_set_init_level(tmp_adev,
359 AMDGPU_INIT_LEVEL_RESET_RECOVERY);
360 dev_info(tmp_adev->dev,
361 "GPU reset succeeded, trying to resume\n");
362 /*TBD: Ideally should clear only GFX, SDMA blocks*/
363 amdgpu_ras_clear_err_state(tmp_adev);
364 r = aldebaran_mode2_restore_ip(tmp_adev);
365 if (r)
366 goto end;
367
368 /*
369 * Add this ASIC as tracked as reset was already
370 * complete successfully.
371 */
372 amdgpu_register_gpu_instance(tmp_adev);
373
374 /* Resume RAS, ecc_irq */
375 con = amdgpu_ras_get_context(tmp_adev);
376 if (!amdgpu_sriov_vf(tmp_adev) && con) {
377 if (tmp_adev->sdma.ras &&
378 tmp_adev->sdma.ras->ras_block.ras_late_init) {
379 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
380 &tmp_adev->sdma.ras->ras_block.ras_comm);
381 if (r) {
382 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r);
383 goto end;
384 }
385 }
386
387 if (tmp_adev->gfx.ras &&
388 tmp_adev->gfx.ras->ras_block.ras_late_init) {
389 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
390 &tmp_adev->gfx.ras->ras_block.ras_comm);
391 if (r) {
392 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r);
393 goto end;
394 }
395 }
396 }
397
398 amdgpu_ras_resume(tmp_adev);
399
400 /* Update PSP FW topology after reset */
401 if (reset_context->hive &&
402 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
403 r = amdgpu_xgmi_update_topology(reset_context->hive,
404 tmp_adev);
405
406 if (!r) {
407 amdgpu_set_init_level(tmp_adev,
408 AMDGPU_INIT_LEVEL_DEFAULT);
409 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
410
411 r = amdgpu_ib_ring_tests(tmp_adev);
412 if (r) {
413 dev_err(tmp_adev->dev,
414 "ib ring test failed (%d).\n", r);
415 r = -EAGAIN;
416 tmp_adev->asic_reset_res = r;
417 goto end;
418 }
419 }
420 }
421
422 end:
423 return r;
424 }
425
426 static struct amdgpu_reset_handler aldebaran_mode2_handler = {
427 .reset_method = AMD_RESET_METHOD_MODE2,
428 .prepare_env = NULL,
429 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
430 .perform_reset = aldebaran_mode2_perform_reset,
431 .restore_hwcontext = aldebaran_mode2_restore_hwcontext,
432 .restore_env = NULL,
433 .do_reset = aldebaran_mode2_reset,
434 };
435
436 static struct amdgpu_reset_handler
437 *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
438 &aldebaran_mode2_handler,
439 &xgmi_reset_on_init_handler,
440 };
441
aldebaran_reset_init(struct amdgpu_device * adev)442 int aldebaran_reset_init(struct amdgpu_device *adev)
443 {
444 struct amdgpu_reset_control *reset_ctl;
445
446 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
447 if (!reset_ctl)
448 return -ENOMEM;
449
450 reset_ctl->handle = adev;
451 reset_ctl->async_reset = aldebaran_async_reset;
452 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
453 reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
454
455 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
456 /* Only mode2 is handled through reset control now */
457 reset_ctl->reset_handlers = &aldebaran_rst_handlers;
458
459 adev->reset_cntl = reset_ctl;
460
461 return 0;
462 }
463
aldebaran_reset_fini(struct amdgpu_device * adev)464 int aldebaran_reset_fini(struct amdgpu_device *adev)
465 {
466 kfree(adev->reset_cntl);
467 adev->reset_cntl = NULL;
468 return 0;
469 }
470