1 /*
2 * Copyright 2025 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "amdgpu_ip.h"
26
amdgpu_logical_to_dev_inst(struct amdgpu_device * adev,enum amd_hw_ip_block_type block,int8_t inst)27 static int8_t amdgpu_logical_to_dev_inst(struct amdgpu_device *adev,
28 enum amd_hw_ip_block_type block,
29 int8_t inst)
30 {
31 int8_t dev_inst;
32
33 switch (block) {
34 case GC_HWIP:
35 case SDMA0_HWIP:
36 /* Both JPEG and VCN as JPEG is only alias of VCN */
37 case VCN_HWIP:
38 dev_inst = adev->ip_map.dev_inst[block][inst];
39 break;
40 default:
41 /* For rest of the IPs, no look up required.
42 * Assume 'logical instance == physical instance' for all configs. */
43 dev_inst = inst;
44 break;
45 }
46
47 return dev_inst;
48 }
49
amdgpu_logical_to_dev_mask(struct amdgpu_device * adev,enum amd_hw_ip_block_type block,uint32_t mask)50 static uint32_t amdgpu_logical_to_dev_mask(struct amdgpu_device *adev,
51 enum amd_hw_ip_block_type block,
52 uint32_t mask)
53 {
54 uint32_t dev_mask = 0;
55 int8_t log_inst, dev_inst;
56
57 while (mask) {
58 log_inst = ffs(mask) - 1;
59 dev_inst = amdgpu_logical_to_dev_inst(adev, block, log_inst);
60 dev_mask |= (1 << dev_inst);
61 mask &= ~(1 << log_inst);
62 }
63
64 return dev_mask;
65 }
66
amdgpu_populate_ip_map(struct amdgpu_device * adev,enum amd_hw_ip_block_type ip_block,uint32_t inst_mask)67 static void amdgpu_populate_ip_map(struct amdgpu_device *adev,
68 enum amd_hw_ip_block_type ip_block,
69 uint32_t inst_mask)
70 {
71 int l = 0, i;
72
73 while (inst_mask) {
74 i = ffs(inst_mask) - 1;
75 adev->ip_map.dev_inst[ip_block][l++] = i;
76 inst_mask &= ~(1 << i);
77 }
78 for (; l < HWIP_MAX_INSTANCE; l++)
79 adev->ip_map.dev_inst[ip_block][l] = -1;
80 }
81
amdgpu_ip_map_init(struct amdgpu_device * adev)82 void amdgpu_ip_map_init(struct amdgpu_device *adev)
83 {
84 u32 ip_map[][2] = {
85 { GC_HWIP, adev->gfx.xcc_mask },
86 { SDMA0_HWIP, adev->sdma.sdma_mask },
87 { VCN_HWIP, adev->vcn.inst_mask },
88 };
89 int i;
90
91 for (i = 0; i < ARRAY_SIZE(ip_map); ++i)
92 amdgpu_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]);
93
94 adev->ip_map.logical_to_dev_inst = amdgpu_logical_to_dev_inst;
95 adev->ip_map.logical_to_dev_mask = amdgpu_logical_to_dev_mask;
96 }
97