1 /* 2 * Copyright 2016-2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HWSS_DCN10_H__ 27 #define __DC_HWSS_DCN10_H__ 28 29 #include "core_types.h" 30 #include "hw_sequencer_private.h" 31 32 struct dc; 33 34 void dcn10_hw_sequencer_construct(struct dc *dc); 35 36 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); 37 void dcn10_calc_vupdate_position( 38 struct dc *dc, 39 struct pipe_ctx *pipe_ctx, 40 uint32_t *start_line, 41 uint32_t *end_line); 42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); 43 enum dc_status dcn10_enable_stream_timing( 44 struct pipe_ctx *pipe_ctx, 45 struct dc_state *context, 46 struct dc *dc); 47 void dcn10_optimize_bandwidth( 48 struct dc *dc, 49 struct dc_state *context); 50 void dcn10_prepare_bandwidth( 51 struct dc *dc, 52 struct dc_state *context); 53 void dcn10_wait_for_pipe_update_if_needed( 54 struct dc *dc, 55 struct pipe_ctx *pipe_ctx, 56 bool is_surface_update_only); 57 void dcn10_set_wait_for_update_needed_for_pipe( 58 struct dc *dc, 59 struct pipe_ctx *pipe_ctx); 60 void dcn10_pipe_control_lock( 61 struct dc *dc, 62 struct pipe_ctx *pipe, 63 bool lock); 64 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); 65 void dcn10_blank_pixel_data( 66 struct dc *dc, 67 struct pipe_ctx *pipe_ctx, 68 bool blank); 69 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, 70 struct dc_link_settings *link_settings); 71 void dcn10_program_output_csc(struct dc *dc, 72 struct pipe_ctx *pipe_ctx, 73 enum dc_color_space colorspace, 74 uint16_t *matrix, 75 int opp_id); 76 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 77 const struct dc_stream_state *stream); 78 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 79 const struct dc_plane_state *plane_state); 80 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx); 81 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); 82 void dcn10_reset_hw_ctx_wrap( 83 struct dc *dc, 84 struct dc_state *context); 85 void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 86 void dcn10_lock_all_pipes( 87 struct dc *dc, 88 struct dc_state *context, 89 bool lock); 90 void dcn10_post_unlock_program_front_end( 91 struct dc *dc, 92 struct dc_state *context); 93 void dcn10_hubp_pg_control( 94 struct dce_hwseq *hws, 95 unsigned int hubp_inst, 96 bool power_on); 97 void dcn10_dpp_pg_control( 98 struct dce_hwseq *hws, 99 unsigned int dpp_inst, 100 bool power_on); 101 void dcn10_enable_power_gating_plane( 102 struct dce_hwseq *hws, 103 bool enable); 104 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx); 105 void dcn10_disable_vga( 106 struct dce_hwseq *hws); 107 void dcn10_program_pipe( 108 struct dc *dc, 109 struct pipe_ctx *pipe_ctx, 110 struct dc_state *context); 111 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx); 112 void dcn10_init_hw(struct dc *dc); 113 void dcn10_init_pipes(struct dc *dc, struct dc_state *context); 114 void dcn10_power_down_on_boot(struct dc *dc); 115 enum dc_status dce110_apply_ctx_to_hw( 116 struct dc *dc, 117 struct dc_state *context); 118 void dcn10_plane_atomic_disconnect(struct dc *dc, 119 struct dc_state *state, 120 struct pipe_ctx *pipe_ctx); 121 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data); 122 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx); 123 void dce110_power_down(struct dc *dc); 124 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context); 125 void dcn10_enable_timing_synchronization( 126 struct dc *dc, 127 struct dc_state *state, 128 int group_index, 129 int group_size, 130 struct pipe_ctx *grouped_pipes[]); 131 void dcn10_enable_vblanks_synchronization( 132 struct dc *dc, 133 int group_index, 134 int group_size, 135 struct pipe_ctx *grouped_pipes[]); 136 void dcn10_enable_per_frame_crtc_position_reset( 137 struct dc *dc, 138 int group_size, 139 struct pipe_ctx *grouped_pipes[]); 140 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); 141 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx, 142 const uint8_t *custom_sdp_message, 143 unsigned int sdp_message_size); 144 void dce110_blank_stream(struct pipe_ctx *pipe_ctx); 145 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx); 146 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx); 147 bool dcn10_dummy_display_power_gating( 148 struct dc *dc, 149 uint8_t controller_id, 150 struct dc_bios *dcb, 151 enum pipe_gating_control power_gating); 152 void dcn10_set_drr(struct pipe_ctx **pipe_ctx, 153 int num_pipes, struct dc_crtc_timing_adjust adjust); 154 void dcn10_get_position(struct pipe_ctx **pipe_ctx, 155 int num_pipes, 156 struct crtc_position *position); 157 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, 158 int num_pipes, const struct dc_static_screen_params *params); 159 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc); 160 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 161 void dcn10_log_hw_state(struct dc *dc, 162 struct dc_log_buffer_ctx *log_ctx); 163 void dcn10_get_hw_state(struct dc *dc, 164 char *pBuf, 165 unsigned int bufSize, 166 unsigned int mask); 167 void dcn10_clear_status_bits(struct dc *dc, unsigned int mask); 168 void dcn10_wait_for_mpcc_disconnect( 169 struct dc *dc, 170 struct resource_pool *res_pool, 171 struct pipe_ctx *pipe_ctx); 172 void dce110_edp_backlight_control( 173 struct dc_link *link, 174 bool enable); 175 void dce110_edp_wait_for_T12( 176 struct dc_link *link); 177 void dce110_edp_power_control( 178 struct dc_link *link, 179 bool power_up); 180 void dce110_edp_wait_for_hpd_ready( 181 struct dc_link *link, 182 bool power_up); 183 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx); 184 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx); 185 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx); 186 void dcn10_setup_periodic_interrupt( 187 struct dc *dc, 188 struct pipe_ctx *pipe_ctx); 189 enum dc_status dcn10_set_clock(struct dc *dc, 190 enum dc_clock_type clock_type, 191 uint32_t clk_khz, 192 uint32_t stepping); 193 void dcn10_get_clock(struct dc *dc, 194 enum dc_clock_type clock_type, 195 struct dc_clock_config *clock_cfg); 196 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx); 197 void dcn10_bios_golden_init(struct dc *dc); 198 void dcn10_plane_atomic_power_down(struct dc *dc, 199 struct dpp *dpp, 200 struct hubp *hubp); 201 bool dcn10_disconnect_pipes( 202 struct dc *dc, 203 struct dc_state *context); 204 205 void dcn10_wait_for_pending_cleared(struct dc *dc, 206 struct dc_state *context); 207 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx); 208 void dcn10_verify_allow_pstate_change_high(struct dc *dc); 209 210 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits); 211 212 void dcn10_update_visual_confirm_color( 213 struct dc *dc, 214 struct pipe_ctx *pipe_ctx, 215 int mpcc_id); 216 217 void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, 218 struct dc_plane_state *plane_state, 219 bool clear_tiling); 220 221 #endif /* __DC_HWSS_DCN10_H__ */ 222