1 /*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * Implementation of a CRTC class for the HDLCD driver.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/of_graph.h>
14
15 #include <video/pixel_format.h>
16 #include <video/videomode.h>
17
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_fb_dma_helper.h>
22 #include <drm/drm_framebuffer.h>
23 #include <drm/drm_gem_dma_helper.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "hdlcd_drv.h"
29 #include "hdlcd_regs.h"
30
31 /*
32 * The HDLCD controller is a dumb RGB streamer that gets connected to
33 * a single HDMI transmitter or in the case of the ARM Models it gets
34 * emulated by the software that does the actual rendering.
35 *
36 */
37
hdlcd_crtc_cleanup(struct drm_crtc * crtc)38 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
39 {
40 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
41
42 /* stop the controller on cleanup */
43 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
44 drm_crtc_cleanup(crtc);
45 }
46
hdlcd_crtc_enable_vblank(struct drm_crtc * crtc)47 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
48 {
49 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
50 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
51
52 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
53
54 return 0;
55 }
56
hdlcd_crtc_disable_vblank(struct drm_crtc * crtc)57 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
58 {
59 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
60 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
61
62 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
63 }
64
65 static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
66 .destroy = hdlcd_crtc_cleanup,
67 .set_config = drm_atomic_helper_set_config,
68 .page_flip = drm_atomic_helper_page_flip,
69 .reset = drm_atomic_helper_crtc_reset,
70 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
71 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
72 .enable_vblank = hdlcd_crtc_enable_vblank,
73 .disable_vblank = hdlcd_crtc_disable_vblank,
74 };
75
76 static const struct {
77 u32 fourcc;
78 struct pixel_format pixel;
79 } supported_formats[] = {
80 { DRM_FORMAT_RGB565, PIXEL_FORMAT_RGB565 },
81 { DRM_FORMAT_XRGB1555, PIXEL_FORMAT_XRGB1555 },
82 { DRM_FORMAT_RGB888, PIXEL_FORMAT_RGB888 },
83 { DRM_FORMAT_XRGB8888, PIXEL_FORMAT_XRGB8888 },
84 { DRM_FORMAT_XBGR8888, PIXEL_FORMAT_XBGR8888 },
85 { DRM_FORMAT_XRGB2101010, PIXEL_FORMAT_XRGB2101010},
86 };
87
88 /*
89 * Setup the HDLCD registers for decoding the pixels out of the framebuffer
90 */
hdlcd_set_pxl_fmt(struct drm_crtc * crtc)91 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
92 {
93 unsigned int btpp;
94 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
95 const struct drm_framebuffer *fb = crtc->primary->state->fb;
96 const struct pixel_format *format = NULL;
97 int i;
98
99 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
100 if (supported_formats[i].fourcc == fb->format->format)
101 format = &supported_formats[i].pixel;
102 }
103
104 if (WARN_ON(!format))
105 return 0;
106
107 /* HDLCD uses 'bytes per pixel', zero means 1 byte */
108 btpp = (format->bits_per_pixel + 7) / 8;
109 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
110
111 /*
112 * The format of the HDLCD_REG_<color>_SELECT register is:
113 * - bits[23:16] - default value for that color component
114 * - bits[11:8] - number of bits to extract for each color component
115 * - bits[4:0] - index of the lowest bit to extract
116 *
117 * The default color value is used when bits[11:8] are zero, when the
118 * pixel is outside the visible frame area or when there is a
119 * buffer underrun.
120 */
121 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
122 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
123 0x00ff0000 | /* show underruns in red */
124 #endif
125 ((format->red.length & 0xf) << 8));
126 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
127 ((format->green.length & 0xf) << 8));
128 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
129 ((format->blue.length & 0xf) << 8));
130
131 return 0;
132 }
133
hdlcd_crtc_mode_set_nofb(struct drm_crtc * crtc)134 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
135 {
136 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
137 struct drm_display_mode *m = &crtc->state->adjusted_mode;
138 struct videomode vm;
139 unsigned int polarities, err;
140
141 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
142 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
143 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
144 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
145 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
146 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
147
148 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
149
150 if (m->flags & DRM_MODE_FLAG_PHSYNC)
151 polarities |= HDLCD_POLARITY_HSYNC;
152 if (m->flags & DRM_MODE_FLAG_PVSYNC)
153 polarities |= HDLCD_POLARITY_VSYNC;
154
155 /* Allow max number of outstanding requests and largest burst size */
156 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
157 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
158
159 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
160 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
161 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
162 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
163 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
164 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
165 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
166 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
167 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
168
169 err = hdlcd_set_pxl_fmt(crtc);
170 if (err)
171 return;
172
173 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
174 }
175
hdlcd_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)176 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
177 struct drm_atomic_state *state)
178 {
179 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
180
181 clk_prepare_enable(hdlcd->clk);
182 hdlcd_crtc_mode_set_nofb(crtc);
183 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
184 drm_crtc_vblank_on(crtc);
185 }
186
hdlcd_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)187 static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
188 struct drm_atomic_state *state)
189 {
190 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
191
192 drm_crtc_vblank_off(crtc);
193 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
194 clk_disable_unprepare(hdlcd->clk);
195 }
196
hdlcd_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)197 static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
198 const struct drm_display_mode *mode)
199 {
200 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
201 long rate, clk_rate = mode->clock * 1000;
202
203 rate = clk_round_rate(hdlcd->clk, clk_rate);
204 /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
205 if (abs(rate - clk_rate) * 1000 > clk_rate) {
206 /* clock required by mode not supported by hardware */
207 return MODE_NOCLOCK;
208 }
209
210 return MODE_OK;
211 }
212
hdlcd_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)213 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
214 struct drm_atomic_state *state)
215 {
216 struct drm_pending_vblank_event *event = crtc->state->event;
217
218 if (event) {
219 crtc->state->event = NULL;
220
221 spin_lock_irq(&crtc->dev->event_lock);
222 if (drm_crtc_vblank_get(crtc) == 0)
223 drm_crtc_arm_vblank_event(crtc, event);
224 else
225 drm_crtc_send_vblank_event(crtc, event);
226 spin_unlock_irq(&crtc->dev->event_lock);
227 }
228 }
229
230 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
231 .mode_valid = hdlcd_crtc_mode_valid,
232 .atomic_begin = hdlcd_crtc_atomic_begin,
233 .atomic_enable = hdlcd_crtc_atomic_enable,
234 .atomic_disable = hdlcd_crtc_atomic_disable,
235 };
236
hdlcd_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)237 static int hdlcd_plane_atomic_check(struct drm_plane *plane,
238 struct drm_atomic_state *state)
239 {
240 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
241 plane);
242 int i;
243 struct drm_crtc *crtc;
244 struct drm_crtc_state *crtc_state;
245 u32 src_h = new_plane_state->src_h >> 16;
246
247 /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
248 if (src_h >= HDLCD_MAX_YRES) {
249 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
250 return -EINVAL;
251 }
252
253 for_each_new_crtc_in_state(state, crtc, crtc_state,
254 i) {
255 /* we cannot disable the plane while the CRTC is active */
256 if (!new_plane_state->fb && crtc_state->active)
257 return -EINVAL;
258 return drm_atomic_helper_check_plane_state(new_plane_state,
259 crtc_state,
260 DRM_PLANE_NO_SCALING,
261 DRM_PLANE_NO_SCALING,
262 false, true);
263 }
264
265 return 0;
266 }
267
hdlcd_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)268 static void hdlcd_plane_atomic_update(struct drm_plane *plane,
269 struct drm_atomic_state *state)
270 {
271 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
272 plane);
273 struct drm_framebuffer *fb = new_plane_state->fb;
274 struct hdlcd_drm_private *hdlcd;
275 u32 dest_h;
276 dma_addr_t scanout_start;
277
278 if (!fb)
279 return;
280
281 dest_h = drm_rect_height(&new_plane_state->dst);
282 scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0);
283
284 hdlcd = drm_to_hdlcd_priv(plane->dev);
285 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
286 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
287 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
288 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
289 }
290
291 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
292 .atomic_check = hdlcd_plane_atomic_check,
293 .atomic_update = hdlcd_plane_atomic_update,
294 };
295
296 static const struct drm_plane_funcs hdlcd_plane_funcs = {
297 .update_plane = drm_atomic_helper_update_plane,
298 .disable_plane = drm_atomic_helper_disable_plane,
299 .reset = drm_atomic_helper_plane_reset,
300 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
301 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
302 };
303
hdlcd_plane_init(struct drm_device * drm)304 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
305 {
306 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
307 struct drm_plane *plane = NULL;
308 u32 formats[ARRAY_SIZE(supported_formats)], i;
309
310 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
311 formats[i] = supported_formats[i].fourcc;
312
313 plane = drmm_universal_plane_alloc(drm, struct drm_plane, dev, 0xff,
314 &hdlcd_plane_funcs,
315 formats, ARRAY_SIZE(formats),
316 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
317 if (IS_ERR(plane))
318 return plane;
319
320 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
321 hdlcd->plane = plane;
322
323 return plane;
324 }
325
hdlcd_setup_crtc(struct drm_device * drm)326 int hdlcd_setup_crtc(struct drm_device *drm)
327 {
328 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
329 struct drm_plane *primary;
330 int ret;
331
332 primary = hdlcd_plane_init(drm);
333 if (IS_ERR(primary))
334 return PTR_ERR(primary);
335
336 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
337 &hdlcd_crtc_funcs, NULL);
338 if (ret)
339 return ret;
340
341 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
342 return 0;
343 }
344