1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2012 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <linux/delay.h>
30
31 #include "ast_drv.h"
32 #include "ast_post.h"
33
34 /*
35 * POST
36 */
37
ast_2000_set_def_ext_reg(struct ast_device * ast)38 void ast_2000_set_def_ext_reg(struct ast_device *ast)
39 {
40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 u8 i, index, reg;
42 const u8 *ext_reg_info;
43
44 /* reset scratch */
45 for (i = 0x81; i <= 0x9f; i++)
46 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
47
48 ext_reg_info = extreginfo;
49 index = 0xa0;
50 while (*ext_reg_info != 0xff) {
51 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
52 index++;
53 ext_reg_info++;
54 }
55
56 /* disable standard IO/MEM decode if secondary */
57 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
58
59 /* Set Ext. Default */
60 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
62
63 /* Enable RAMDAC for A1 */
64 reg = 0x04;
65 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
66 }
67
68 static const struct ast_dramstruct ast2000_dram_table_data[] = {
69 { 0x0108, 0x00000000 },
70 { 0x0120, 0x00004a21 },
71 AST_DRAMSTRUCT_UDELAY(67u),
72 { 0x0000, 0xFFFFFFFF },
73 AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000089),
74 { 0x0008, 0x22331353 },
75 { 0x000C, 0x0d07000b },
76 { 0x0010, 0x11113333 },
77 { 0x0020, 0x00110350 },
78 { 0x0028, 0x1e0828f0 },
79 { 0x0024, 0x00000001 },
80 { 0x001C, 0x00000000 },
81 { 0x0014, 0x00000003 },
82 AST_DRAMSTRUCT_UDELAY(67u),
83 { 0x0018, 0x00000131 },
84 { 0x0014, 0x00000001 },
85 AST_DRAMSTRUCT_UDELAY(67u),
86 { 0x0018, 0x00000031 },
87 { 0x0014, 0x00000001 },
88 AST_DRAMSTRUCT_UDELAY(67u),
89 { 0x0028, 0x1e0828f1 },
90 { 0x0024, 0x00000003 },
91 { 0x002C, 0x1f0f28fb },
92 { 0x0030, 0xFFFFFE01 },
93 AST_DRAMSTRUCT_INVALID,
94 };
95
ast_post_chip_2000(struct ast_device * ast)96 static void ast_post_chip_2000(struct ast_device *ast)
97 {
98 u8 j;
99 u32 temp, i;
100 const struct ast_dramstruct *dram_reg_info;
101
102 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
103
104 if ((j & 0x80) == 0) { /* VGA only */
105 dram_reg_info = ast2000_dram_table_data;
106 ast_write32(ast, 0xf004, 0x1e6e0000);
107 ast_write32(ast, 0xf000, 0x1);
108 ast_write32(ast, 0x10100, 0xa8);
109
110 do {
111 ;
112 } while (ast_read32(ast, 0x10100) != 0xa8);
113
114 while (!AST_DRAMSTRUCT_IS(dram_reg_info, INVALID)) {
115 if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) {
116 for (i = 0; i < 15; i++)
117 udelay(dram_reg_info->data);
118 } else {
119 ast_write32(ast, 0x10000 + dram_reg_info->index,
120 dram_reg_info->data);
121 }
122 dram_reg_info++;
123 }
124
125 temp = ast_read32(ast, 0x10140);
126 ast_write32(ast, 0x10140, temp | 0x40);
127 }
128
129 /* wait ready */
130 do {
131 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
132 } while ((j & 0x40) == 0);
133 }
134
ast_2000_post(struct ast_device * ast)135 int ast_2000_post(struct ast_device *ast)
136 {
137 ast_2000_set_def_ext_reg(ast);
138
139 if (ast->config_mode == ast_use_p2a) {
140 ast_post_chip_2000(ast);
141 } else {
142 if (ast->tx_chip == AST_TX_SIL164) {
143 /* Enable DVO */
144 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
145 }
146 }
147
148 return 0;
149 }
150