1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 * Author: Vinay Simha <vinaysimha@inforcecomputing.com>
6 */
7
8 #include <linux/delay.h>
9
10 #include <drm/drm_crtc.h>
11 #include <drm/drm_probe_helper.h>
12
13 #include "mdp4_kms.h"
14
15 struct mdp4_lcdc_encoder {
16 struct drm_encoder base;
17 struct drm_panel *panel;
18 struct clk *lcdc_clk;
19 unsigned long int pixclock;
20 struct regulator_bulk_data regs[3];
21 bool enabled;
22 uint32_t bsc;
23 };
24 #define to_mdp4_lcdc_encoder(x) container_of(x, struct mdp4_lcdc_encoder, base)
25
get_kms(struct drm_encoder * encoder)26 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
27 {
28 struct msm_drm_private *priv = encoder->dev->dev_private;
29 return to_mdp4_kms(to_mdp_kms(priv->kms));
30 }
31
32 /* this should probably be a helper: */
get_connector(struct drm_encoder * encoder)33 static struct drm_connector *get_connector(struct drm_encoder *encoder)
34 {
35 struct drm_device *dev = encoder->dev;
36 struct drm_connector *connector;
37
38 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
39 if (connector->encoder == encoder)
40 return connector;
41
42 return NULL;
43 }
44
setup_phy(struct drm_encoder * encoder)45 static void setup_phy(struct drm_encoder *encoder)
46 {
47 struct drm_device *dev = encoder->dev;
48 struct drm_connector *connector = get_connector(encoder);
49 struct mdp4_kms *mdp4_kms = get_kms(encoder);
50 uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0;
51 int bpp, nchan, swap;
52
53 if (!connector)
54 return;
55
56 bpp = 3 * connector->display_info.bpc;
57
58 if (!bpp)
59 bpp = 18;
60
61 /* TODO, these should come from panel somehow: */
62 nchan = 1;
63 swap = 0;
64
65 switch (bpp) {
66 case 24:
67 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
68 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x08) |
69 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x05) |
70 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x04) |
71 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x03));
72 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
73 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x02) |
74 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x01) |
75 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x00));
76 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
77 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x11) |
78 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x10) |
79 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0d) |
80 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0c));
81 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
82 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0b) |
83 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0a) |
84 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x09));
85 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
86 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
87 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
88 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
89 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x15));
90 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
91 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x14) |
92 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x13) |
93 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x12));
94 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3),
95 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1b) |
96 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x17) |
97 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x16) |
98 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0f));
99 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3),
100 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0e) |
101 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x07) |
102 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x06));
103 if (nchan == 2) {
104 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN |
105 MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
106 MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
107 MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
108 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
109 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
110 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
111 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
112 } else {
113 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
114 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
115 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
116 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
117 }
118 break;
119
120 case 18:
121 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
122 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x0a) |
123 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x07) |
124 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x06) |
125 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x05));
126 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
127 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x04) |
128 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x03) |
129 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x02));
130 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
131 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x13) |
132 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x12) |
133 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0f) |
134 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0e));
135 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
136 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0d) |
137 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0c) |
138 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x0b));
139 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
140 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
141 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
142 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
143 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x17));
144 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
145 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x16) |
146 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x15) |
147 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x14));
148 if (nchan == 2) {
149 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
150 MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
151 MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
152 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
153 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
154 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
155 } else {
156 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
157 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
158 MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
159 }
160 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT;
161 break;
162
163 default:
164 DRM_DEV_ERROR(dev->dev, "unknown bpp: %d\n", bpp);
165 return;
166 }
167
168 switch (nchan) {
169 case 1:
170 lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0;
171 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN |
172 MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL;
173 break;
174 case 2:
175 lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0 |
176 MDP4_LVDS_PHY_CFG0_CHANNEL1;
177 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN |
178 MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN;
179 break;
180 default:
181 DRM_DEV_ERROR(dev->dev, "unknown # of channels: %d\n", nchan);
182 return;
183 }
184
185 if (swap)
186 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP;
187
188 lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_ENABLE;
189
190 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
191 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf);
192 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30);
193
194 mb();
195 udelay(1);
196 lvds_phy_cfg0 |= MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE;
197 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
198 }
199
mdp4_lcdc_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)200 static void mdp4_lcdc_encoder_mode_set(struct drm_encoder *encoder,
201 struct drm_display_mode *mode,
202 struct drm_display_mode *adjusted_mode)
203 {
204 struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
205 to_mdp4_lcdc_encoder(encoder);
206 struct mdp4_kms *mdp4_kms = get_kms(encoder);
207 uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol;
208 uint32_t display_v_start, display_v_end;
209 uint32_t hsync_start_x, hsync_end_x;
210
211 mode = adjusted_mode;
212
213 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
214
215 mdp4_lcdc_encoder->pixclock = mode->clock * 1000;
216
217 DBG("pixclock=%lu", mdp4_lcdc_encoder->pixclock);
218
219 ctrl_pol = 0;
220 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
221 ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW;
222 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
223 ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW;
224 /* probably need to get DATA_EN polarity from panel.. */
225
226 lcdc_hsync_skew = 0; /* get this from panel? */
227
228 hsync_start_x = (mode->htotal - mode->hsync_start);
229 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
230
231 vsync_period = mode->vtotal * mode->htotal;
232 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
233 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew;
234 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_skew - 1;
235
236 mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL,
237 MDP4_LCDC_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
238 MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal));
239 mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period);
240 mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len);
241 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL,
242 MDP4_LCDC_DISPLAY_HCTRL_START(hsync_start_x) |
243 MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x));
244 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start);
245 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end);
246 mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0);
247 mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR,
248 MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY |
249 MDP4_LCDC_UNDERFLOW_CLR_COLOR(0xff));
250 mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew);
251 mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol);
252 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL,
253 MDP4_LCDC_ACTIVE_HCTL_START(0) |
254 MDP4_LCDC_ACTIVE_HCTL_END(0));
255 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0);
256 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0);
257 }
258
mdp4_lcdc_encoder_disable(struct drm_encoder * encoder)259 static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)
260 {
261 struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
262 to_mdp4_lcdc_encoder(encoder);
263 struct mdp4_kms *mdp4_kms = get_kms(encoder);
264
265 if (WARN_ON(!mdp4_lcdc_encoder->enabled))
266 return;
267
268 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
269
270 /*
271 * Wait for a vsync so we know the ENABLE=0 latched before
272 * the (connector) source of the vsync's gets disabled,
273 * otherwise we end up in a funny state if we re-enable
274 * before the disable latches, which results that some of
275 * the settings changes for the new modeset (like new
276 * scanout buffer) don't latch properly..
277 */
278 mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);
279
280 clk_disable_unprepare(mdp4_lcdc_encoder->lcdc_clk);
281
282 regulator_bulk_disable(ARRAY_SIZE(mdp4_lcdc_encoder->regs),
283 mdp4_lcdc_encoder->regs);
284
285 mdp4_lcdc_encoder->enabled = false;
286 }
287
mdp4_lcdc_encoder_enable(struct drm_encoder * encoder)288 static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
289 {
290 struct drm_device *dev = encoder->dev;
291 struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
292 to_mdp4_lcdc_encoder(encoder);
293 unsigned long pc = mdp4_lcdc_encoder->pixclock;
294 struct mdp4_kms *mdp4_kms = get_kms(encoder);
295 uint32_t config;
296 int ret;
297
298 if (WARN_ON(mdp4_lcdc_encoder->enabled))
299 return;
300
301 /* TODO: hard-coded for 18bpp: */
302 config =
303 MDP4_DMA_CONFIG_R_BPC(BPC6) |
304 MDP4_DMA_CONFIG_G_BPC(BPC6) |
305 MDP4_DMA_CONFIG_B_BPC(BPC6) |
306 MDP4_DMA_CONFIG_PACK(0x21) |
307 MDP4_DMA_CONFIG_DEFLKR_EN |
308 MDP4_DMA_CONFIG_DITHER_EN;
309
310 if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb"))
311 config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB;
312
313 mdp4_crtc_set_config(encoder->crtc, config);
314 mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);
315
316 ret = regulator_bulk_enable(ARRAY_SIZE(mdp4_lcdc_encoder->regs),
317 mdp4_lcdc_encoder->regs);
318 if (ret)
319 DRM_DEV_ERROR(dev->dev, "failed to enable regulators: %d\n", ret);
320
321 DBG("setting lcdc_clk=%lu", pc);
322 ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
323 if (ret)
324 DRM_DEV_ERROR(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
325 ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
326 if (ret)
327 DRM_DEV_ERROR(dev->dev, "failed to enable lcdc_clk: %d\n", ret);
328
329 setup_phy(encoder);
330
331 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);
332
333 mdp4_lcdc_encoder->enabled = true;
334 }
335
336 static enum drm_mode_status
mdp4_lcdc_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)337 mdp4_lcdc_encoder_mode_valid(struct drm_encoder *encoder,
338 const struct drm_display_mode *mode)
339 {
340 struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
341 to_mdp4_lcdc_encoder(encoder);
342 long actual, requested;
343
344 requested = 1000 * mode->clock;
345 actual = clk_round_rate(mdp4_lcdc_encoder->lcdc_clk, requested);
346
347 DBG("requested=%ld, actual=%ld", requested, actual);
348
349 if (actual != requested)
350 return MODE_CLOCK_RANGE;
351
352 return MODE_OK;
353 }
354
355 static const struct drm_encoder_helper_funcs mdp4_lcdc_encoder_helper_funcs = {
356 .mode_set = mdp4_lcdc_encoder_mode_set,
357 .disable = mdp4_lcdc_encoder_disable,
358 .enable = mdp4_lcdc_encoder_enable,
359 .mode_valid = mdp4_lcdc_encoder_mode_valid,
360 };
361
362 /* initialize encoder */
mdp4_lcdc_encoder_init(struct drm_device * dev)363 struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev)
364 {
365 struct drm_encoder *encoder;
366 struct mdp4_lcdc_encoder *mdp4_lcdc_encoder;
367 int ret;
368
369 mdp4_lcdc_encoder = drmm_encoder_alloc(dev, struct mdp4_lcdc_encoder, base,
370 NULL, DRM_MODE_ENCODER_LVDS, NULL);
371 if (IS_ERR(mdp4_lcdc_encoder))
372 return ERR_CAST(mdp4_lcdc_encoder);
373
374 encoder = &mdp4_lcdc_encoder->base;
375
376 drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs);
377
378 mdp4_lcdc_encoder->lcdc_clk = mpd4_get_lcdc_clock(dev);
379 if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
380 DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n");
381 return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk);
382 }
383
384 /* TODO: different regulators in other cases? */
385 mdp4_lcdc_encoder->regs[0].supply = "lvds-vccs-3p3v";
386 mdp4_lcdc_encoder->regs[1].supply = "lvds-pll-vdda";
387 mdp4_lcdc_encoder->regs[2].supply = "lvds-vdda";
388
389 ret = devm_regulator_bulk_get(dev->dev,
390 ARRAY_SIZE(mdp4_lcdc_encoder->regs),
391 mdp4_lcdc_encoder->regs);
392 if (ret)
393 return ERR_PTR(ret);
394
395 return encoder;
396 }
397