1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NV3051D MIPI-DSI panel driver for Anbernic RG353x
4  * Copyright (C) 2022 Chris Morgan
5  *
6  * based on
7  *
8  * Elida kd35t133 3.5" MIPI-DSI panel driver
9  * Copyright (C) Theobroma Systems 2020
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/media-bus-format.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/regulator/consumer.h>
18 
19 #include <video/display_timing.h>
20 #include <video/mipi_display.h>
21 
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_modes.h>
24 #include <drm/drm_panel.h>
25 
26 struct nv3051d_panel_info {
27 	const struct drm_display_mode *display_modes;
28 	unsigned int num_modes;
29 	u16 width_mm, height_mm;
30 	u32 bus_flags;
31 	u32 mode_flags;
32 };
33 
34 struct panel_nv3051d {
35 	struct device *dev;
36 	struct drm_panel panel;
37 	struct gpio_desc *reset_gpio;
38 	const struct nv3051d_panel_info *panel_info;
39 	struct regulator *vdd;
40 };
41 
panel_to_panelnv3051d(struct drm_panel * panel)42 static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel *panel)
43 {
44 	return container_of(panel, struct panel_nv3051d, panel);
45 }
46 
panel_nv3051d_init_sequence(struct panel_nv3051d * ctx)47 static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx)
48 {
49 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
50 	struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi};
51 
52 	/*
53 	 * Init sequence was supplied by device vendor with no
54 	 * documentation.
55 	 */
56 
57 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30);
58 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52);
59 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x01);
60 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x00);
61 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);
62 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x00);
63 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x03);
64 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x12);
65 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x1E);
66 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x28);
67 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x52);
68 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x57);
69 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x01);
70 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0xDF);
71 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x9C);
72 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0xA7);
73 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x53);
74 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);
75 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x3C);
76 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xFE);
77 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x00);
78 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x77);
79 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x77);
80 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA0, 0x55);
81 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA1, 0x50);
82 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA4, 0x9C);
83 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA7, 0x02);
84 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA8, 0x01);
85 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA9, 0x01);
86 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAA, 0xFC);
87 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAB, 0x28);
88 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAC, 0x06);
89 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAD, 0x06);
90 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAE, 0x06);
91 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAF, 0x03);
92 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB0, 0x08);
93 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x26);
94 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB2, 0x28);
95 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, 0x28);
96 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x33);
97 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x08);
98 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x26);
99 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x08);
100 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x26);
101 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30);
102 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52);
103 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x02);
104 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x0E);
105 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD1, 0x0E);
106 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x29);
107 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD4, 0x2B);
108 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB2, 0x0C);
109 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD2, 0x0A);
110 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, 0x28);
111 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD3, 0x28);
112 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x11);
113 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD6, 0x0D);
114 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x32);
115 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD7, 0x30);
116 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC1, 0x04);
117 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x06);
118 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x0A);
119 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD8, 0x0A);
120 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB9, 0x01);
121 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD9, 0x01);
122 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBD, 0x13);
123 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDD, 0x13);
124 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBC, 0x11);
125 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDC, 0x11);
126 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBB, 0x0F);
127 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDB, 0x0F);
128 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBA, 0x0F);
129 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDA, 0x0F);
130 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBE, 0x18);
131 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDE, 0x18);
132 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBF, 0x0F);
133 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDF, 0x0F);
134 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC0, 0x17);
135 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x17);
136 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x3B);
137 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD5, 0x3C);
138 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB0, 0x0B);
139 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD0, 0x0C);
140 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30);
141 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52);
142 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x03);
143 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x2A);
144 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x2A);
145 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x2A);
146 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x2A);
147 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x61);
148 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x80);
149 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0xC7);
150 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x01);
151 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x82);
152 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x83);
153 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x2A);
154 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x2A);
155 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x2A);
156 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x2A);
157 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x61);
158 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0xC5);
159 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x80);
160 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x23);
161 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x82);
162 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x83);
163 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x80);
164 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x81);
165 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x11);
166 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0xF2);
167 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0xF1);
168 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x11);
169 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0xF4);
170 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0xF3);
171 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x02);
172 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x01);
173 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x04);
174 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x03);
175 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x11);
176 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0xF6);
177 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0xF5);
178 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x11);
179 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0xF8);
180 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xF7);
181 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x02);
182 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x80);
183 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x5A);
184 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x00);
185 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x0E);
186 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x0F);
187 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x04);
188 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x07);
189 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x06);
190 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB9, 0x05);
191 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBA, 0x0F);
192 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC7, 0x00);
193 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCA, 0x0E);
194 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCB, 0x0F);
195 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCC, 0x04);
196 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCD, 0x07);
197 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCE, 0x06);
198 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCF, 0x05);
199 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD0, 0x0F);
200 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F);
201 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x0E);
202 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x0F);
203 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x07);
204 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x04);
205 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x05);
206 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0x06);
207 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8A, 0x00);
208 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0x0F);
209 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9A, 0x0E);
210 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9B, 0x0F);
211 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9C, 0x07);
212 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9D, 0x04);
213 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9E, 0x05);
214 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x06);
215 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA0, 0x00);
216 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30);
217 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52);
218 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x02);
219 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x01);
220 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xDA);
221 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0xBA);
222 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0xA8);
223 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x9A);
224 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x70);
225 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0xFF);
226 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x91);
227 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x90);
228 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0xFF);
229 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x8F);
230 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x60);
231 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x58);
232 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48);
233 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x38);
234 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x2B);
235 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30);
236 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52);
237 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x00);
238 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x02);
239 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x70);
240 
241 	dev_dbg(ctx->dev, "Panel init sequence done\n");
242 
243 	return 0;
244 }
245 
panel_nv3051d_unprepare(struct drm_panel * panel)246 static int panel_nv3051d_unprepare(struct drm_panel *panel)
247 {
248 	struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
249 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
250 	int ret;
251 
252 	ret = mipi_dsi_dcs_set_display_off(dsi);
253 	if (ret < 0)
254 		dev_err(ctx->dev, "failed to set display off: %d\n", ret);
255 
256 	msleep(20);
257 
258 	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
259 	if (ret < 0) {
260 		dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret);
261 		return ret;
262 	}
263 
264 	usleep_range(10000, 15000);
265 
266 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
267 
268 	regulator_disable(ctx->vdd);
269 
270 	return 0;
271 }
272 
panel_nv3051d_prepare(struct drm_panel * panel)273 static int panel_nv3051d_prepare(struct drm_panel *panel)
274 {
275 	struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
276 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
277 	int ret;
278 
279 	dev_dbg(ctx->dev, "Resetting the panel\n");
280 	ret = regulator_enable(ctx->vdd);
281 	if (ret < 0) {
282 		dev_err(ctx->dev, "Failed to enable vdd supply: %d\n", ret);
283 		return ret;
284 	}
285 
286 	usleep_range(2000, 3000);
287 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
288 	msleep(150);
289 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
290 	msleep(20);
291 
292 	ret = panel_nv3051d_init_sequence(ctx);
293 	if (ret < 0) {
294 		dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
295 		goto disable_vdd;
296 	}
297 
298 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
299 	if (ret < 0) {
300 		dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
301 		goto disable_vdd;
302 	}
303 
304 	msleep(200);
305 
306 	ret = mipi_dsi_dcs_set_display_on(dsi);
307 	if (ret < 0) {
308 		dev_err(ctx->dev, "Failed to set display on: %d\n", ret);
309 		goto disable_vdd;
310 	}
311 
312 	usleep_range(10000, 15000);
313 
314 	return 0;
315 
316 disable_vdd:
317 	regulator_disable(ctx->vdd);
318 	return ret;
319 }
320 
panel_nv3051d_get_modes(struct drm_panel * panel,struct drm_connector * connector)321 static int panel_nv3051d_get_modes(struct drm_panel *panel,
322 				   struct drm_connector *connector)
323 {
324 	struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
325 	const struct nv3051d_panel_info *panel_info = ctx->panel_info;
326 	struct drm_display_mode *mode;
327 	unsigned int i;
328 
329 	for (i = 0; i < panel_info->num_modes; i++) {
330 		mode = drm_mode_duplicate(connector->dev,
331 					  &panel_info->display_modes[i]);
332 		if (!mode)
333 			return -ENOMEM;
334 
335 		drm_mode_set_name(mode);
336 
337 		mode->type = DRM_MODE_TYPE_DRIVER;
338 		if (panel_info->num_modes == 1)
339 			mode->type |= DRM_MODE_TYPE_PREFERRED;
340 
341 		drm_mode_probed_add(connector, mode);
342 	}
343 
344 	connector->display_info.bpc = 8;
345 	connector->display_info.width_mm = panel_info->width_mm;
346 	connector->display_info.height_mm = panel_info->height_mm;
347 	connector->display_info.bus_flags = panel_info->bus_flags;
348 
349 	return panel_info->num_modes;
350 }
351 
352 static const struct drm_panel_funcs panel_nv3051d_funcs = {
353 	.unprepare	= panel_nv3051d_unprepare,
354 	.prepare	= panel_nv3051d_prepare,
355 	.get_modes	= panel_nv3051d_get_modes,
356 };
357 
panel_nv3051d_probe(struct mipi_dsi_device * dsi)358 static int panel_nv3051d_probe(struct mipi_dsi_device *dsi)
359 {
360 	struct device *dev = &dsi->dev;
361 	struct panel_nv3051d *ctx;
362 	int ret;
363 
364 	ctx = devm_drm_panel_alloc(dev, struct panel_nv3051d, panel,
365 				   &panel_nv3051d_funcs,
366 				   DRM_MODE_CONNECTOR_DSI);
367 	if (IS_ERR(ctx))
368 		return PTR_ERR(ctx);
369 
370 	ctx->dev = dev;
371 
372 	ctx->panel_info = of_device_get_match_data(dev);
373 	if (!ctx->panel_info)
374 		return -EINVAL;
375 
376 	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
377 	if (IS_ERR(ctx->reset_gpio)) {
378 		dev_err(dev, "cannot get reset gpio\n");
379 		return PTR_ERR(ctx->reset_gpio);
380 	}
381 
382 	ctx->vdd = devm_regulator_get(dev, "vdd");
383 	if (IS_ERR(ctx->vdd)) {
384 		ret = PTR_ERR(ctx->vdd);
385 		if (ret != -EPROBE_DEFER)
386 			dev_err(dev, "Failed to request vdd regulator: %d\n", ret);
387 		return ret;
388 	}
389 
390 	mipi_dsi_set_drvdata(dsi, ctx);
391 
392 	dsi->lanes = 4;
393 	dsi->format = MIPI_DSI_FMT_RGB888;
394 	dsi->mode_flags = ctx->panel_info->mode_flags;
395 
396 	ret = drm_panel_of_backlight(&ctx->panel);
397 	if (ret)
398 		return ret;
399 
400 	drm_panel_add(&ctx->panel);
401 
402 	ret = mipi_dsi_attach(dsi);
403 	if (ret < 0) {
404 		dev_err(dev, "mipi_dsi_attach failed: %d\n", ret);
405 		drm_panel_remove(&ctx->panel);
406 		return ret;
407 	}
408 
409 	return 0;
410 }
411 
panel_nv3051d_shutdown(struct mipi_dsi_device * dsi)412 static void panel_nv3051d_shutdown(struct mipi_dsi_device *dsi)
413 {
414 	struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi);
415 
416 	drm_panel_unprepare(&ctx->panel);
417 
418 	drm_panel_disable(&ctx->panel);
419 }
420 
panel_nv3051d_remove(struct mipi_dsi_device * dsi)421 static void panel_nv3051d_remove(struct mipi_dsi_device *dsi)
422 {
423 	struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi);
424 	int ret;
425 
426 	panel_nv3051d_shutdown(dsi);
427 
428 	ret = mipi_dsi_detach(dsi);
429 	if (ret < 0)
430 		dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
431 
432 	drm_panel_remove(&ctx->panel);
433 }
434 
435 static const struct drm_display_mode nv3051d_rgxx3_modes[] = {
436 	{ /* 120hz */
437 		.hdisplay	= 640,
438 		.hsync_start	= 640 + 40,
439 		.hsync_end	= 640 + 40 + 2,
440 		.htotal		= 640 + 40 + 2 + 80,
441 		.vdisplay	= 480,
442 		.vsync_start	= 480 + 18,
443 		.vsync_end	= 480 + 18 + 2,
444 		.vtotal		= 480 + 18 + 2 + 28,
445 		.clock		= 48300,
446 		.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
447 	},
448 	{ /* 100hz */
449 		.hdisplay       = 640,
450 		.hsync_start    = 640 + 40,
451 		.hsync_end      = 640 + 40 + 2,
452 		.htotal         = 640 + 40 + 2 + 80,
453 		.vdisplay       = 480,
454 		.vsync_start    = 480 + 18,
455 		.vsync_end      = 480 + 18 + 2,
456 		.vtotal         = 480 + 18 + 2 + 28,
457 		.clock          = 40250,
458 		.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
459 	},
460 	{ /* 60hz */
461 		.hdisplay	= 640,
462 		.hsync_start	= 640 + 40,
463 		.hsync_end	= 640 + 40 + 2,
464 		.htotal		= 640 + 40 + 2 + 80,
465 		.vdisplay	= 480,
466 		.vsync_start	= 480 + 18,
467 		.vsync_end	= 480 + 18 + 2,
468 		.vtotal		= 480 + 18 + 2 + 28,
469 		.clock		= 24150,
470 		.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
471 	},
472 };
473 
474 static const struct drm_display_mode nv3051d_rk2023_modes[] = {
475 	{
476 		.hdisplay       = 640,
477 		.hsync_start    = 640 + 40,
478 		.hsync_end      = 640 + 40 + 2,
479 		.htotal         = 640 + 40 + 2 + 80,
480 		.vdisplay       = 480,
481 		.vsync_start    = 480 + 18,
482 		.vsync_end      = 480 + 18 + 2,
483 		.vtotal         = 480 + 18 + 2 + 4,
484 		.clock          = 24150,
485 		.flags          = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
486 	},
487 };
488 
489 static const struct nv3051d_panel_info nv3051d_rg351v_info = {
490 	.display_modes = nv3051d_rgxx3_modes,
491 	.num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes),
492 	.width_mm = 70,
493 	.height_mm = 57,
494 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
495 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
496 		      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET |
497 		      MIPI_DSI_CLOCK_NON_CONTINUOUS,
498 };
499 
500 static const struct nv3051d_panel_info nv3051d_rg353p_info = {
501 	.display_modes = nv3051d_rgxx3_modes,
502 	.num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes),
503 	.width_mm = 70,
504 	.height_mm = 57,
505 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
506 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
507 		      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
508 };
509 
510 static const struct nv3051d_panel_info nv3051d_rk2023_info = {
511 	.display_modes = nv3051d_rk2023_modes,
512 	.num_modes = ARRAY_SIZE(nv3051d_rk2023_modes),
513 	.width_mm = 70,
514 	.height_mm = 57,
515 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
516 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
517 		      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
518 };
519 
520 static const struct of_device_id newvision_nv3051d_of_match[] = {
521 	{ .compatible = "anbernic,rg351v-panel", .data = &nv3051d_rg351v_info },
522 	{ .compatible = "anbernic,rg353p-panel", .data = &nv3051d_rg353p_info },
523 	{ .compatible = "powkiddy,rk2023-panel", .data = &nv3051d_rk2023_info },
524 	{ /* sentinel */ }
525 };
526 MODULE_DEVICE_TABLE(of, newvision_nv3051d_of_match);
527 
528 static struct mipi_dsi_driver newvision_nv3051d_driver = {
529 	.driver = {
530 		.name = "panel-newvision-nv3051d",
531 		.of_match_table = newvision_nv3051d_of_match,
532 	},
533 	.probe	= panel_nv3051d_probe,
534 	.remove = panel_nv3051d_remove,
535 	.shutdown = panel_nv3051d_shutdown,
536 };
537 module_mipi_dsi_driver(newvision_nv3051d_driver);
538 
539 MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>");
540 MODULE_DESCRIPTION("DRM driver for Newvision NV3051D based MIPI DSI panels");
541 MODULE_LICENSE("GPL");
542