1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
6 #include <drm/drm_atomic.h>
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_blend.h>
9 #include <drm/drm_crtc.h>
10 #include <drm/drm_fb_dma_helper.h>
11 #include <drm/drm_framebuffer.h>
12 #include <drm/drm_gem_atomic_helper.h>
13 #include <drm/drm_gem_dma_helper.h>
14 #include <drm/drm_probe_helper.h>
15
16 #include "sun8i_csc.h"
17 #include "sun8i_mixer.h"
18 #include "sun8i_vi_layer.h"
19 #include "sun8i_vi_scaler.h"
20
sun8i_vi_layer_update_alpha(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane)21 static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
22 int overlay, struct drm_plane *plane)
23 {
24 u32 mask, val, ch_base;
25
26 ch_base = sun8i_channel_base(mixer, channel);
27
28 if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
29 mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK |
30 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK;
31 val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA
32 (plane->state->alpha >> 8);
33
34 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
35 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
36 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED;
37
38 regmap_update_bits(mixer->engine.regs,
39 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base,
40 overlay),
41 mask, val);
42 } else if (mixer->cfg->vi_num == 1) {
43 regmap_update_bits(mixer->engine.regs,
44 SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
45 SUN8I_MIXER_FCC_GLOBAL_ALPHA_MASK,
46 SUN8I_MIXER_FCC_GLOBAL_ALPHA
47 (plane->state->alpha >> 8));
48 }
49 }
50
sun8i_vi_layer_update_coord(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane,unsigned int zpos)51 static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
52 int overlay, struct drm_plane *plane,
53 unsigned int zpos)
54 {
55 struct drm_plane_state *state = plane->state;
56 const struct drm_format_info *format = state->fb->format;
57 u32 src_w, src_h, dst_w, dst_h;
58 struct regmap *bld_regs;
59 u32 bld_base, ch_base;
60 u32 outsize, insize;
61 u32 hphase, vphase;
62 u32 hn = 0, hm = 0;
63 u32 vn = 0, vm = 0;
64 bool subsampled;
65
66 DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
67 channel, overlay);
68
69 bld_base = sun8i_blender_base(mixer);
70 bld_regs = sun8i_blender_regmap(mixer);
71 ch_base = sun8i_channel_base(mixer, channel);
72
73 src_w = drm_rect_width(&state->src) >> 16;
74 src_h = drm_rect_height(&state->src) >> 16;
75 dst_w = drm_rect_width(&state->dst);
76 dst_h = drm_rect_height(&state->dst);
77
78 hphase = state->src.x1 & 0xffff;
79 vphase = state->src.y1 & 0xffff;
80
81 /* make coordinates dividable by subsampling factor */
82 if (format->hsub > 1) {
83 int mask, remainder;
84
85 mask = format->hsub - 1;
86 remainder = (state->src.x1 >> 16) & mask;
87 src_w = (src_w + remainder) & ~mask;
88 hphase += remainder << 16;
89 }
90
91 if (format->vsub > 1) {
92 int mask, remainder;
93
94 mask = format->vsub - 1;
95 remainder = (state->src.y1 >> 16) & mask;
96 src_h = (src_h + remainder) & ~mask;
97 vphase += remainder << 16;
98 }
99
100 insize = SUN8I_MIXER_SIZE(src_w, src_h);
101 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
102
103 /* Set height and width */
104 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
105 (state->src.x1 >> 16) & ~(format->hsub - 1),
106 (state->src.y1 >> 16) & ~(format->vsub - 1));
107 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
108 regmap_write(mixer->engine.regs,
109 SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
110 insize);
111 regmap_write(mixer->engine.regs,
112 SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
113 insize);
114
115 /*
116 * Scaler must be enabled for subsampled formats, so it scales
117 * chroma to same size as luma.
118 */
119 subsampled = format->hsub > 1 || format->vsub > 1;
120
121 if (insize != outsize || subsampled || hphase || vphase) {
122 unsigned int scanline, required;
123 struct drm_display_mode *mode;
124 u32 hscale, vscale, fps;
125 u64 ability;
126
127 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
128
129 mode = &plane->state->crtc->state->mode;
130 fps = (mode->clock * 1000) / (mode->vtotal * mode->htotal);
131 ability = clk_get_rate(mixer->mod_clk);
132 /* BSP algorithm assumes 80% efficiency of VI scaler unit */
133 ability *= 80;
134 do_div(ability, mode->vdisplay * fps * max(src_w, dst_w));
135
136 required = src_h * 100 / dst_h;
137
138 if (ability < required) {
139 DRM_DEBUG_DRIVER("Using vertical coarse scaling\n");
140 vm = src_h;
141 vn = (u32)ability * dst_h / 100;
142 src_h = vn;
143 }
144
145 /* it seems that every RGB scaler has buffer for 2048 pixels */
146 scanline = subsampled ? mixer->cfg->scanline_yuv : 2048;
147
148 if (src_w > scanline) {
149 DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
150 hm = src_w;
151 hn = scanline;
152 src_w = hn;
153 }
154
155 hscale = (src_w << 16) / dst_w;
156 vscale = (src_h << 16) / dst_h;
157
158 sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
159 dst_h, hscale, vscale, hphase, vphase,
160 format);
161 sun8i_vi_scaler_enable(mixer, channel, true);
162 } else {
163 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
164 sun8i_vi_scaler_enable(mixer, channel, false);
165 }
166
167 regmap_write(mixer->engine.regs,
168 SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base),
169 SUN8I_MIXER_CHAN_VI_DS_N(hn) |
170 SUN8I_MIXER_CHAN_VI_DS_M(hm));
171 regmap_write(mixer->engine.regs,
172 SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base),
173 SUN8I_MIXER_CHAN_VI_DS_N(hn) |
174 SUN8I_MIXER_CHAN_VI_DS_M(hm));
175 regmap_write(mixer->engine.regs,
176 SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base),
177 SUN8I_MIXER_CHAN_VI_DS_N(vn) |
178 SUN8I_MIXER_CHAN_VI_DS_M(vm));
179 regmap_write(mixer->engine.regs,
180 SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),
181 SUN8I_MIXER_CHAN_VI_DS_N(vn) |
182 SUN8I_MIXER_CHAN_VI_DS_M(vm));
183
184 /* Set base coordinates */
185 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
186 state->dst.x1, state->dst.y1);
187 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
188 regmap_write(bld_regs,
189 SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
190 SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
191 regmap_write(bld_regs,
192 SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
193 outsize);
194
195 return 0;
196 }
197
sun8i_vi_layer_get_csc_mode(const struct drm_format_info * format)198 static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *format)
199 {
200 if (!format->is_yuv)
201 return SUN8I_CSC_MODE_OFF;
202
203 switch (format->format) {
204 case DRM_FORMAT_YVU411:
205 case DRM_FORMAT_YVU420:
206 case DRM_FORMAT_YVU422:
207 case DRM_FORMAT_YVU444:
208 return SUN8I_CSC_MODE_YVU2RGB;
209 default:
210 return SUN8I_CSC_MODE_YUV2RGB;
211 }
212 }
213
sun8i_vi_layer_update_formats(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane)214 static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
215 int overlay, struct drm_plane *plane)
216 {
217 struct drm_plane_state *state = plane->state;
218 u32 val, ch_base, csc_mode, hw_fmt;
219 const struct drm_format_info *fmt;
220 int ret;
221
222 ch_base = sun8i_channel_base(mixer, channel);
223
224 fmt = state->fb->format;
225 ret = sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
226 if (ret) {
227 DRM_DEBUG_DRIVER("Invalid format\n");
228 return ret;
229 }
230
231 val = hw_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
232 regmap_update_bits(mixer->engine.regs,
233 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
234 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
235
236 csc_mode = sun8i_vi_layer_get_csc_mode(fmt);
237 if (csc_mode != SUN8I_CSC_MODE_OFF) {
238 sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode,
239 state->color_encoding,
240 state->color_range);
241 sun8i_csc_enable_ccsc(mixer, channel, true);
242 } else {
243 sun8i_csc_enable_ccsc(mixer, channel, false);
244 }
245
246 if (!fmt->is_yuv)
247 val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
248 else
249 val = 0;
250
251 regmap_update_bits(mixer->engine.regs,
252 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
253 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
254
255 return 0;
256 }
257
sun8i_vi_layer_update_buffer(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane)258 static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
259 int overlay, struct drm_plane *plane)
260 {
261 struct drm_plane_state *state = plane->state;
262 struct drm_framebuffer *fb = state->fb;
263 const struct drm_format_info *format = fb->format;
264 struct drm_gem_dma_object *gem;
265 u32 dx, dy, src_x, src_y;
266 dma_addr_t dma_addr;
267 u32 ch_base;
268 int i;
269
270 ch_base = sun8i_channel_base(mixer, channel);
271
272 /* Adjust x and y to be dividable by subsampling factor */
273 src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
274 src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
275
276 for (i = 0; i < format->num_planes; i++) {
277 /* Get the physical address of the buffer in memory */
278 gem = drm_fb_dma_get_gem_obj(fb, i);
279
280 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr);
281
282 /* Compute the start of the displayed memory */
283 dma_addr = gem->dma_addr + fb->offsets[i];
284
285 dx = src_x;
286 dy = src_y;
287
288 if (i > 0) {
289 dx /= format->hsub;
290 dy /= format->vsub;
291 }
292
293 /* Fixup framebuffer address for src coordinates */
294 dma_addr += dx * format->cpp[i];
295 dma_addr += dy * fb->pitches[i];
296
297 /* Set the line width */
298 DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
299 i + 1, fb->pitches[i]);
300 regmap_write(mixer->engine.regs,
301 SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
302 overlay, i),
303 fb->pitches[i]);
304
305 DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
306 i + 1, &dma_addr);
307
308 regmap_write(mixer->engine.regs,
309 SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
310 overlay, i),
311 lower_32_bits(dma_addr));
312 }
313
314 return 0;
315 }
316
sun8i_vi_layer_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)317 static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
318 struct drm_atomic_state *state)
319 {
320 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
321 plane);
322 struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
323 struct drm_crtc *crtc = new_plane_state->crtc;
324 struct drm_crtc_state *crtc_state;
325 int min_scale, max_scale;
326
327 if (!crtc)
328 return 0;
329
330 crtc_state = drm_atomic_get_existing_crtc_state(state,
331 crtc);
332 if (WARN_ON(!crtc_state))
333 return -EINVAL;
334
335 min_scale = DRM_PLANE_NO_SCALING;
336 max_scale = DRM_PLANE_NO_SCALING;
337
338 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
339 min_scale = SUN8I_VI_SCALER_SCALE_MIN;
340 max_scale = SUN8I_VI_SCALER_SCALE_MAX;
341 }
342
343 return drm_atomic_helper_check_plane_state(new_plane_state,
344 crtc_state,
345 min_scale, max_scale,
346 true, true);
347 }
348
sun8i_vi_layer_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)349 static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
350 struct drm_atomic_state *state)
351 {
352 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
353 plane);
354 struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
355 unsigned int zpos = new_state->normalized_zpos;
356 struct sun8i_mixer *mixer = layer->mixer;
357
358 if (!new_state->crtc || !new_state->visible)
359 return;
360
361 sun8i_vi_layer_update_coord(mixer, layer->channel,
362 layer->overlay, plane, zpos);
363 sun8i_vi_layer_update_alpha(mixer, layer->channel,
364 layer->overlay, plane);
365 sun8i_vi_layer_update_formats(mixer, layer->channel,
366 layer->overlay, plane);
367 sun8i_vi_layer_update_buffer(mixer, layer->channel,
368 layer->overlay, plane);
369 }
370
371 static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
372 .atomic_check = sun8i_vi_layer_atomic_check,
373 .atomic_update = sun8i_vi_layer_atomic_update,
374 };
375
376 static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
377 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
378 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
379 .destroy = drm_plane_cleanup,
380 .disable_plane = drm_atomic_helper_disable_plane,
381 .reset = drm_atomic_helper_plane_reset,
382 .update_plane = drm_atomic_helper_update_plane,
383 };
384
385 /*
386 * While DE2 VI layer supports same RGB formats as UI layer, alpha
387 * channel is ignored. This structure lists all unique variants
388 * where alpha channel is replaced with "don't care" (X) channel.
389 */
390 static const u32 sun8i_vi_layer_formats[] = {
391 DRM_FORMAT_BGR565,
392 DRM_FORMAT_BGR888,
393 DRM_FORMAT_BGRX4444,
394 DRM_FORMAT_BGRX5551,
395 DRM_FORMAT_BGRX8888,
396 DRM_FORMAT_RGB565,
397 DRM_FORMAT_RGB888,
398 DRM_FORMAT_RGBX4444,
399 DRM_FORMAT_RGBX5551,
400 DRM_FORMAT_RGBX8888,
401 DRM_FORMAT_XBGR1555,
402 DRM_FORMAT_XBGR4444,
403 DRM_FORMAT_XBGR8888,
404 DRM_FORMAT_XRGB1555,
405 DRM_FORMAT_XRGB4444,
406 DRM_FORMAT_XRGB8888,
407
408 DRM_FORMAT_NV16,
409 DRM_FORMAT_NV12,
410 DRM_FORMAT_NV21,
411 DRM_FORMAT_NV61,
412 DRM_FORMAT_UYVY,
413 DRM_FORMAT_VYUY,
414 DRM_FORMAT_YUYV,
415 DRM_FORMAT_YVYU,
416 DRM_FORMAT_YUV411,
417 DRM_FORMAT_YUV420,
418 DRM_FORMAT_YUV422,
419 DRM_FORMAT_YVU411,
420 DRM_FORMAT_YVU420,
421 DRM_FORMAT_YVU422,
422 };
423
424 static const u32 sun8i_vi_layer_de3_formats[] = {
425 DRM_FORMAT_ABGR1555,
426 DRM_FORMAT_ABGR2101010,
427 DRM_FORMAT_ABGR4444,
428 DRM_FORMAT_ABGR8888,
429 DRM_FORMAT_ARGB1555,
430 DRM_FORMAT_ARGB2101010,
431 DRM_FORMAT_ARGB4444,
432 DRM_FORMAT_ARGB8888,
433 DRM_FORMAT_BGR565,
434 DRM_FORMAT_BGR888,
435 DRM_FORMAT_BGRA1010102,
436 DRM_FORMAT_BGRA5551,
437 DRM_FORMAT_BGRA4444,
438 DRM_FORMAT_BGRA8888,
439 DRM_FORMAT_BGRX8888,
440 DRM_FORMAT_RGB565,
441 DRM_FORMAT_RGB888,
442 DRM_FORMAT_RGBA1010102,
443 DRM_FORMAT_RGBA4444,
444 DRM_FORMAT_RGBA5551,
445 DRM_FORMAT_RGBA8888,
446 DRM_FORMAT_RGBX8888,
447 DRM_FORMAT_XBGR8888,
448 DRM_FORMAT_XRGB8888,
449
450 DRM_FORMAT_NV16,
451 DRM_FORMAT_NV12,
452 DRM_FORMAT_NV21,
453 DRM_FORMAT_NV61,
454 DRM_FORMAT_P010,
455 DRM_FORMAT_P210,
456 DRM_FORMAT_UYVY,
457 DRM_FORMAT_VYUY,
458 DRM_FORMAT_YUYV,
459 DRM_FORMAT_YVYU,
460 DRM_FORMAT_YUV411,
461 DRM_FORMAT_YUV420,
462 DRM_FORMAT_YUV422,
463 DRM_FORMAT_YVU411,
464 DRM_FORMAT_YVU420,
465 DRM_FORMAT_YVU422,
466 };
467
468 static const uint64_t sun8i_layer_modifiers[] = {
469 DRM_FORMAT_MOD_LINEAR,
470 DRM_FORMAT_MOD_INVALID
471 };
472
sun8i_vi_layer_init_one(struct drm_device * drm,struct sun8i_mixer * mixer,int index)473 struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
474 struct sun8i_mixer *mixer,
475 int index)
476 {
477 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
478 u32 supported_encodings, supported_ranges;
479 unsigned int plane_cnt, format_count;
480 struct sun8i_layer *layer;
481 const u32 *formats;
482 int ret;
483
484 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
485 if (!layer)
486 return ERR_PTR(-ENOMEM);
487
488 if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
489 formats = sun8i_vi_layer_de3_formats;
490 format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
491 } else {
492 formats = sun8i_vi_layer_formats;
493 format_count = ARRAY_SIZE(sun8i_vi_layer_formats);
494 }
495
496 if (!mixer->cfg->ui_num && index == 0)
497 type = DRM_PLANE_TYPE_PRIMARY;
498
499 /* possible crtcs are set later */
500 ret = drm_universal_plane_init(drm, &layer->plane, 0,
501 &sun8i_vi_layer_funcs,
502 formats, format_count,
503 sun8i_layer_modifiers,
504 type, NULL);
505 if (ret) {
506 dev_err(drm->dev, "Couldn't initialize layer\n");
507 return ERR_PTR(ret);
508 }
509
510 plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
511
512 if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
513 ret = drm_plane_create_alpha_property(&layer->plane);
514 if (ret) {
515 dev_err(drm->dev, "Couldn't add alpha property\n");
516 return ERR_PTR(ret);
517 }
518 }
519
520 ret = drm_plane_create_zpos_property(&layer->plane, index,
521 0, plane_cnt - 1);
522 if (ret) {
523 dev_err(drm->dev, "Couldn't add zpos property\n");
524 return ERR_PTR(ret);
525 }
526
527 supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
528 BIT(DRM_COLOR_YCBCR_BT709);
529 if (mixer->cfg->de_type >= SUN8I_MIXER_DE3)
530 supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
531
532 supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
533 BIT(DRM_COLOR_YCBCR_FULL_RANGE);
534
535 ret = drm_plane_create_color_properties(&layer->plane,
536 supported_encodings,
537 supported_ranges,
538 DRM_COLOR_YCBCR_BT709,
539 DRM_COLOR_YCBCR_LIMITED_RANGE);
540 if (ret) {
541 dev_err(drm->dev, "Couldn't add encoding and range properties!\n");
542 return ERR_PTR(ret);
543 }
544
545 drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
546 layer->mixer = mixer;
547 layer->type = SUN8I_LAYER_TYPE_VI;
548 layer->channel = index;
549 layer->overlay = 0;
550
551 return layer;
552 }
553