1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include "iris_core.h"
7 #include "iris_ctrls.h"
8 #include "iris_hfi_gen2.h"
9 #include "iris_hfi_gen2_defines.h"
10 #include "iris_platform_common.h"
11 #include "iris_vpu_common.h"
12
13 #include "iris_platform_qcs8300.h"
14 #include "iris_platform_sm8650.h"
15
16 #define VIDEO_ARCH_LX 1
17
18 static struct platform_inst_fw_cap inst_fw_cap_sm8550[] = {
19 {
20 .cap_id = PROFILE_H264,
21 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
22 .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
23 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
24 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
25 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
26 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
27 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
28 .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
29 .hfi_id = HFI_PROP_PROFILE,
30 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
31 .set = iris_set_u32_enum,
32 },
33 {
34 .cap_id = PROFILE_HEVC,
35 .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
36 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
37 .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
38 BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
39 .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
40 .hfi_id = HFI_PROP_PROFILE,
41 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
42 .set = iris_set_u32_enum,
43 },
44 {
45 .cap_id = PROFILE_VP9,
46 .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
47 .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
48 .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
49 BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
50 .value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
51 .hfi_id = HFI_PROP_PROFILE,
52 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
53 .set = iris_set_u32_enum,
54 },
55 {
56 .cap_id = LEVEL_H264,
57 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
58 .max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
59 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
60 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
61 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
62 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
63 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
64 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
65 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
66 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
67 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
68 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
69 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
70 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
71 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
72 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
73 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
74 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
75 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
76 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
77 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
78 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
79 .value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
80 .hfi_id = HFI_PROP_LEVEL,
81 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
82 .set = iris_set_u32_enum,
83 },
84 {
85 .cap_id = LEVEL_HEVC,
86 .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
87 .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
88 .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
89 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
90 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
91 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
92 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
93 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
94 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
95 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
96 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
97 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
98 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
99 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
100 BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
101 .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
102 .hfi_id = HFI_PROP_LEVEL,
103 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
104 .set = iris_set_u32_enum,
105 },
106 {
107 .cap_id = LEVEL_VP9,
108 .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
109 .max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
110 .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
111 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
112 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
113 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
114 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
115 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
116 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
117 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
118 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
119 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
120 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
121 BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
122 .value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
123 .hfi_id = HFI_PROP_LEVEL,
124 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
125 .set = iris_set_u32_enum,
126 },
127 {
128 .cap_id = TIER,
129 .min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
130 .max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
131 .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
132 BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
133 .value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
134 .hfi_id = HFI_PROP_TIER,
135 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
136 .set = iris_set_u32_enum,
137 },
138 {
139 .cap_id = INPUT_BUF_HOST_MAX_COUNT,
140 .min = DEFAULT_MAX_HOST_BUF_COUNT,
141 .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
142 .step_or_mask = 1,
143 .value = DEFAULT_MAX_HOST_BUF_COUNT,
144 .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
145 .flags = CAP_FLAG_INPUT_PORT,
146 .set = iris_set_u32,
147 },
148 {
149 .cap_id = STAGE,
150 .min = STAGE_1,
151 .max = STAGE_2,
152 .step_or_mask = 1,
153 .value = STAGE_2,
154 .hfi_id = HFI_PROP_STAGE,
155 .set = iris_set_stage,
156 },
157 {
158 .cap_id = PIPE,
159 .min = PIPE_1,
160 .max = PIPE_4,
161 .step_or_mask = 1,
162 .value = PIPE_4,
163 .hfi_id = HFI_PROP_PIPE,
164 .set = iris_set_pipe,
165 },
166 {
167 .cap_id = POC,
168 .min = 0,
169 .max = 2,
170 .step_or_mask = 1,
171 .value = 1,
172 .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
173 },
174 {
175 .cap_id = CODED_FRAMES,
176 .min = CODED_FRAMES_PROGRESSIVE,
177 .max = CODED_FRAMES_PROGRESSIVE,
178 .step_or_mask = 0,
179 .value = CODED_FRAMES_PROGRESSIVE,
180 .hfi_id = HFI_PROP_CODED_FRAMES,
181 },
182 {
183 .cap_id = BIT_DEPTH,
184 .min = BIT_DEPTH_8,
185 .max = BIT_DEPTH_8,
186 .step_or_mask = 1,
187 .value = BIT_DEPTH_8,
188 .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
189 },
190 {
191 .cap_id = RAP_FRAME,
192 .min = 0,
193 .max = 1,
194 .step_or_mask = 1,
195 .value = 1,
196 .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
197 .flags = CAP_FLAG_INPUT_PORT,
198 .set = iris_set_u32,
199 },
200 };
201
202 static struct platform_inst_caps platform_inst_cap_sm8550 = {
203 .min_frame_width = 96,
204 .max_frame_width = 8192,
205 .min_frame_height = 96,
206 .max_frame_height = 8192,
207 .max_mbpf = (8192 * 4352) / 256,
208 .mb_cycles_vpp = 200,
209 .mb_cycles_fw = 489583,
210 .mb_cycles_fw_vpp = 66234,
211 .num_comv = 0,
212 };
213
iris_set_sm8550_preset_registers(struct iris_core * core)214 static void iris_set_sm8550_preset_registers(struct iris_core *core)
215 {
216 writel(0x0, core->reg_base + 0xB0088);
217 }
218
219 static const struct icc_info sm8550_icc_table[] = {
220 { "cpu-cfg", 1000, 1000 },
221 { "video-mem", 1000, 15000000 },
222 };
223
224 static const char * const sm8550_clk_reset_table[] = { "bus" };
225
226 static const struct bw_info sm8550_bw_table_dec[] = {
227 { ((4096 * 2160) / 256) * 60, 1608000 },
228 { ((4096 * 2160) / 256) * 30, 826000 },
229 { ((1920 * 1080) / 256) * 60, 567000 },
230 { ((1920 * 1080) / 256) * 30, 294000 },
231 };
232
233 static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
234
235 static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
236
237 static const struct platform_clk_data sm8550_clk_table[] = {
238 {IRIS_AXI_CLK, "iface" },
239 {IRIS_CTRL_CLK, "core" },
240 {IRIS_HW_CLK, "vcodec0_core" },
241 };
242
243 static struct ubwc_config_data ubwc_config_sm8550 = {
244 .max_channels = 8,
245 .mal_length = 32,
246 .highest_bank_bit = 16,
247 .bank_swzl_level = 0,
248 .bank_swz2_level = 1,
249 .bank_swz3_level = 1,
250 .bank_spreading = 1,
251 };
252
253 static struct tz_cp_config tz_cp_config_sm8550 = {
254 .cp_start = 0,
255 .cp_size = 0x25800000,
256 .cp_nonpixel_start = 0x01000000,
257 .cp_nonpixel_size = 0x24800000,
258 };
259
260 static const u32 sm8550_vdec_input_config_params_default[] = {
261 HFI_PROP_BITSTREAM_RESOLUTION,
262 HFI_PROP_CROP_OFFSETS,
263 HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
264 HFI_PROP_CODED_FRAMES,
265 HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
266 HFI_PROP_PIC_ORDER_CNT_TYPE,
267 HFI_PROP_PROFILE,
268 HFI_PROP_LEVEL,
269 HFI_PROP_SIGNAL_COLOR_INFO,
270 };
271
272 static const u32 sm8550_vdec_input_config_param_hevc[] = {
273 HFI_PROP_BITSTREAM_RESOLUTION,
274 HFI_PROP_CROP_OFFSETS,
275 HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
276 HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
277 HFI_PROP_PROFILE,
278 HFI_PROP_LEVEL,
279 HFI_PROP_TIER,
280 HFI_PROP_SIGNAL_COLOR_INFO,
281 };
282
283 static const u32 sm8550_vdec_input_config_param_vp9[] = {
284 HFI_PROP_BITSTREAM_RESOLUTION,
285 HFI_PROP_CROP_OFFSETS,
286 HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
287 HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
288 HFI_PROP_PROFILE,
289 HFI_PROP_LEVEL,
290 };
291
292 static const u32 sm8550_vdec_output_config_params[] = {
293 HFI_PROP_COLOR_FORMAT,
294 HFI_PROP_LINEAR_STRIDE_SCANLINE,
295 };
296
297 static const u32 sm8550_vdec_subscribe_input_properties[] = {
298 HFI_PROP_NO_OUTPUT,
299 };
300
301 static const u32 sm8550_vdec_subscribe_output_properties_avc[] = {
302 HFI_PROP_PICTURE_TYPE,
303 HFI_PROP_CABAC_SESSION,
304 };
305
306 static const u32 sm8550_vdec_subscribe_output_properties_hevc[] = {
307 HFI_PROP_PICTURE_TYPE,
308 };
309
310 static const u32 sm8550_vdec_subscribe_output_properties_vp9[] = {
311 HFI_PROP_PICTURE_TYPE,
312 };
313
314 static const u32 sm8550_dec_ip_int_buf_tbl[] = {
315 BUF_BIN,
316 BUF_COMV,
317 BUF_NON_COMV,
318 BUF_LINE,
319 };
320
321 static const u32 sm8550_dec_op_int_buf_tbl[] = {
322 BUF_DPB,
323 };
324
325 struct iris_platform_data sm8550_data = {
326 .get_instance = iris_hfi_gen2_get_instance,
327 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
328 .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
329 .vpu_ops = &iris_vpu3_ops,
330 .set_preset_registers = iris_set_sm8550_preset_registers,
331 .icc_tbl = sm8550_icc_table,
332 .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
333 .clk_rst_tbl = sm8550_clk_reset_table,
334 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
335 .bw_tbl_dec = sm8550_bw_table_dec,
336 .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
337 .pmdomain_tbl = sm8550_pmdomain_table,
338 .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
339 .opp_pd_tbl = sm8550_opp_pd_table,
340 .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
341 .clk_tbl = sm8550_clk_table,
342 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
343 /* Upper bound of DMA address range */
344 .dma_mask = 0xe0000000 - 1,
345 .fwname = "qcom/vpu/vpu30_p4.mbn",
346 .pas_id = IRIS_PAS_ID,
347 .inst_caps = &platform_inst_cap_sm8550,
348 .inst_fw_caps = inst_fw_cap_sm8550,
349 .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550),
350 .tz_cp_config_data = &tz_cp_config_sm8550,
351 .core_arch = VIDEO_ARCH_LX,
352 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
353 .ubwc_config = &ubwc_config_sm8550,
354 .num_vpp_pipe = 4,
355 .max_session_count = 16,
356 .max_core_mbpf = NUM_MBS_8K * 2,
357 .input_config_params_default =
358 sm8550_vdec_input_config_params_default,
359 .input_config_params_default_size =
360 ARRAY_SIZE(sm8550_vdec_input_config_params_default),
361 .input_config_params_hevc =
362 sm8550_vdec_input_config_param_hevc,
363 .input_config_params_hevc_size =
364 ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
365 .input_config_params_vp9 =
366 sm8550_vdec_input_config_param_vp9,
367 .input_config_params_vp9_size =
368 ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
369 .output_config_params =
370 sm8550_vdec_output_config_params,
371 .output_config_params_size =
372 ARRAY_SIZE(sm8550_vdec_output_config_params),
373 .dec_input_prop = sm8550_vdec_subscribe_input_properties,
374 .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
375 .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
376 .dec_output_prop_avc_size =
377 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
378 .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
379 .dec_output_prop_hevc_size =
380 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
381 .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
382 .dec_output_prop_vp9_size =
383 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
384
385 .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
386 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
387 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
388 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
389 };
390
391 /*
392 * Shares most of SM8550 data except:
393 * - vpu_ops to iris_vpu33_ops
394 * - clk_rst_tbl to sm8650_clk_reset_table
395 * - controller_rst_tbl to sm8650_controller_reset_table
396 * - fwname to "qcom/vpu/vpu33_p4.mbn"
397 */
398 struct iris_platform_data sm8650_data = {
399 .get_instance = iris_hfi_gen2_get_instance,
400 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
401 .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
402 .vpu_ops = &iris_vpu33_ops,
403 .set_preset_registers = iris_set_sm8550_preset_registers,
404 .icc_tbl = sm8550_icc_table,
405 .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
406 .clk_rst_tbl = sm8650_clk_reset_table,
407 .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
408 .controller_rst_tbl = sm8650_controller_reset_table,
409 .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
410 .bw_tbl_dec = sm8550_bw_table_dec,
411 .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
412 .pmdomain_tbl = sm8550_pmdomain_table,
413 .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
414 .opp_pd_tbl = sm8550_opp_pd_table,
415 .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
416 .clk_tbl = sm8550_clk_table,
417 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
418 /* Upper bound of DMA address range */
419 .dma_mask = 0xe0000000 - 1,
420 .fwname = "qcom/vpu/vpu33_p4.mbn",
421 .pas_id = IRIS_PAS_ID,
422 .inst_caps = &platform_inst_cap_sm8550,
423 .inst_fw_caps = inst_fw_cap_sm8550,
424 .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550),
425 .tz_cp_config_data = &tz_cp_config_sm8550,
426 .core_arch = VIDEO_ARCH_LX,
427 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
428 .ubwc_config = &ubwc_config_sm8550,
429 .num_vpp_pipe = 4,
430 .max_session_count = 16,
431 .max_core_mbpf = NUM_MBS_8K * 2,
432 .input_config_params_default =
433 sm8550_vdec_input_config_params_default,
434 .input_config_params_default_size =
435 ARRAY_SIZE(sm8550_vdec_input_config_params_default),
436 .input_config_params_hevc =
437 sm8550_vdec_input_config_param_hevc,
438 .input_config_params_hevc_size =
439 ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
440 .input_config_params_vp9 =
441 sm8550_vdec_input_config_param_vp9,
442 .input_config_params_vp9_size =
443 ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
444 .output_config_params =
445 sm8550_vdec_output_config_params,
446 .output_config_params_size =
447 ARRAY_SIZE(sm8550_vdec_output_config_params),
448 .dec_input_prop = sm8550_vdec_subscribe_input_properties,
449 .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
450 .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
451 .dec_output_prop_avc_size =
452 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
453 .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
454 .dec_output_prop_hevc_size =
455 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
456 .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
457 .dec_output_prop_vp9_size =
458 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
459
460 .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
461 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
462 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
463 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
464 };
465
466 /*
467 * Shares most of SM8550 data except:
468 * - inst_caps to platform_inst_cap_qcs8300
469 * - inst_fw_caps to inst_fw_cap_qcs8300
470 */
471 struct iris_platform_data qcs8300_data = {
472 .get_instance = iris_hfi_gen2_get_instance,
473 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
474 .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
475 .vpu_ops = &iris_vpu3_ops,
476 .set_preset_registers = iris_set_sm8550_preset_registers,
477 .icc_tbl = sm8550_icc_table,
478 .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
479 .clk_rst_tbl = sm8550_clk_reset_table,
480 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
481 .bw_tbl_dec = sm8550_bw_table_dec,
482 .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
483 .pmdomain_tbl = sm8550_pmdomain_table,
484 .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
485 .opp_pd_tbl = sm8550_opp_pd_table,
486 .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
487 .clk_tbl = sm8550_clk_table,
488 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
489 /* Upper bound of DMA address range */
490 .dma_mask = 0xe0000000 - 1,
491 .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
492 .pas_id = IRIS_PAS_ID,
493 .inst_caps = &platform_inst_cap_qcs8300,
494 .inst_fw_caps = inst_fw_cap_qcs8300,
495 .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_qcs8300),
496 .tz_cp_config_data = &tz_cp_config_sm8550,
497 .core_arch = VIDEO_ARCH_LX,
498 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
499 .ubwc_config = &ubwc_config_sm8550,
500 .num_vpp_pipe = 2,
501 .max_session_count = 16,
502 .max_core_mbpf = ((4096 * 2176) / 256) * 4,
503 .input_config_params_default =
504 sm8550_vdec_input_config_params_default,
505 .input_config_params_default_size =
506 ARRAY_SIZE(sm8550_vdec_input_config_params_default),
507 .input_config_params_hevc =
508 sm8550_vdec_input_config_param_hevc,
509 .input_config_params_hevc_size =
510 ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
511 .input_config_params_vp9 =
512 sm8550_vdec_input_config_param_vp9,
513 .input_config_params_vp9_size =
514 ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
515 .output_config_params =
516 sm8550_vdec_output_config_params,
517 .output_config_params_size =
518 ARRAY_SIZE(sm8550_vdec_output_config_params),
519 .dec_input_prop = sm8550_vdec_subscribe_input_properties,
520 .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
521 .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
522 .dec_output_prop_avc_size =
523 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
524 .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
525 .dec_output_prop_hevc_size =
526 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
527 .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
528 .dec_output_prop_vp9_size =
529 ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
530
531 .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
532 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
533 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
534 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
535 };
536