1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/firmware.h>
4 #include <linux/module.h>
5 #include <linux/of_address.h>
6 #include <linux/of_platform.h>
7 #include <linux/pinctrl/consumer.h>
8 #include <linux/phy.h>
9
10 #include "mtk.h"
11
12 #define MTK_2P5GPHY_ID_MT7988 0x00339c11
13
14 #define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin"
15 #define MT7988_2P5GE_PMB_FW_SIZE 0x20000
16 #define MT7988_2P5GE_PMB_FW_BASE 0x0f100000
17 #define MT7988_2P5GE_PMB_FW_LEN 0x20000
18 #define MTK_2P5GPHY_MCU_CSR_BASE 0x0f0f0000
19 #define MTK_2P5GPHY_MCU_CSR_LEN 0x20
20 #define MD32_EN_CFG 0x18
21 #define MD32_EN BIT(0)
22
23 #define BASE100T_STATUS_EXTEND 0x10
24 #define BASE1000T_STATUS_EXTEND 0x11
25 #define EXTEND_CTRL_AND_STATUS 0x16
26
27 #define PHY_AUX_CTRL_STATUS 0x1d
28 #define PHY_AUX_DPX_MASK GENMASK(5, 5)
29 #define PHY_AUX_SPEED_MASK GENMASK(4, 2)
30
31 /* Registers on MDIO_MMD_VEND1 */
32 #define MTK_PHY_LPI_PCS_DSP_CTRL 0x121
33 #define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
34
35 #define MTK_PHY_HOST_CMD1 0x800e
36 #define MTK_PHY_HOST_CMD2 0x800f
37 /* Registers on Token Ring debug nodes */
38 /* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
39 #define AUTO_NP_10XEN BIT(6)
40
41 enum {
42 PHY_AUX_SPD_10 = 0,
43 PHY_AUX_SPD_100,
44 PHY_AUX_SPD_1000,
45 PHY_AUX_SPD_2500,
46 };
47
mt798x_2p5ge_phy_load_fw(struct phy_device * phydev)48 static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
49 {
50 struct device *dev = &phydev->mdio.dev;
51 void __iomem *mcu_csr_base, *pmb_addr;
52 const struct firmware *fw;
53 int ret, i;
54 u32 reg;
55
56 pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
57 if (!pmb_addr)
58 return -ENOMEM;
59 mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE,
60 MTK_2P5GPHY_MCU_CSR_LEN);
61 if (!mcu_csr_base) {
62 ret = -ENOMEM;
63 goto free_pmb;
64 }
65
66 ret = request_firmware_direct(&fw, MT7988_2P5GE_PMB_FW, dev);
67 if (ret) {
68 dev_err(dev, "failed to load firmware: %s, ret: %d\n",
69 MT7988_2P5GE_PMB_FW, ret);
70 goto free;
71 }
72
73 if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
74 dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
75 fw->size, MT7988_2P5GE_PMB_FW_SIZE);
76 ret = -EINVAL;
77 goto release_fw;
78 }
79
80 reg = readw(mcu_csr_base + MD32_EN_CFG);
81 if (reg & MD32_EN) {
82 phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
83 usleep_range(10000, 11000);
84 }
85 phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
86
87 /* Write magic number to safely stall MCU */
88 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100);
89 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df);
90
91 for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
92 writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
93
94 writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
95 writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
96 phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
97 /* We need a delay here to stabilize initialization of MCU */
98 usleep_range(7000, 8000);
99
100 dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
101 be16_to_cpu(*((__be16 *)(fw->data +
102 MT7988_2P5GE_PMB_FW_SIZE - 8))),
103 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
104 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
105 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
106 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
107
108 release_fw:
109 release_firmware(fw);
110 free:
111 iounmap(mcu_csr_base);
112 free_pmb:
113 iounmap(pmb_addr);
114
115 return ret;
116 }
117
mt798x_2p5ge_phy_config_init(struct phy_device * phydev)118 static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
119 {
120 /* Check if PHY interface type is compatible */
121 if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
122 return -ENODEV;
123
124 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
125 MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
126
127 /* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */
128 mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
129 FIELD_PREP(AUTO_NP_10XEN, 0x1));
130
131 /* Enable HW auto downshift */
132 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
133 MTK_PHY_AUX_CTRL_AND_STATUS,
134 0, MTK_PHY_ENABLE_DOWNSHIFT);
135
136 return 0;
137 }
138
mt798x_2p5ge_phy_config_aneg(struct phy_device * phydev)139 static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
140 {
141 bool changed = false;
142 u32 adv;
143 int ret;
144
145 ret = genphy_c45_an_config_aneg(phydev);
146 if (ret < 0)
147 return ret;
148 if (ret > 0)
149 changed = true;
150
151 /* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
152 * our design.
153 */
154 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
155 ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
156 if (ret < 0)
157 return ret;
158 if (ret > 0)
159 changed = true;
160
161 return genphy_c45_check_and_restart_aneg(phydev, changed);
162 }
163
mt798x_2p5ge_phy_get_features(struct phy_device * phydev)164 static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
165 {
166 int ret;
167
168 ret = genphy_c45_pma_read_abilities(phydev);
169 if (ret)
170 return ret;
171
172 /* This phy can't handle collision, and neither can (XFI)MAC it's
173 * connected to. Although it can do HDX handshake, it doesn't support
174 * CSMA/CD that HDX requires.
175 */
176 linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
177 phydev->supported);
178
179 return 0;
180 }
181
mt798x_2p5ge_phy_read_status(struct phy_device * phydev)182 static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
183 {
184 int ret;
185
186 /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy
187 * actually hasn't finished AN. So use CL22's link update function
188 * instead.
189 */
190 ret = genphy_update_link(phydev);
191 if (ret)
192 return ret;
193
194 phydev->speed = SPEED_UNKNOWN;
195 phydev->duplex = DUPLEX_UNKNOWN;
196 phydev->pause = 0;
197 phydev->asym_pause = 0;
198
199 /* We'll read link speed through vendor specific registers down below.
200 * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma
201 * (AN off).
202 */
203 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
204 ret = genphy_c45_read_lpa(phydev);
205 if (ret < 0)
206 return ret;
207
208 /* Clause 45 doesn't define 1000BaseT support. Read the link
209 * partner's 1G advertisement via Clause 22.
210 */
211 ret = phy_read(phydev, MII_STAT1000);
212 if (ret < 0)
213 return ret;
214 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
215 } else if (phydev->autoneg == AUTONEG_DISABLE) {
216 linkmode_zero(phydev->lp_advertising);
217 }
218
219 if (phydev->link) {
220 ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
221 if (ret < 0)
222 return ret;
223
224 switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
225 case PHY_AUX_SPD_10:
226 phydev->speed = SPEED_10;
227 break;
228 case PHY_AUX_SPD_100:
229 phydev->speed = SPEED_100;
230 break;
231 case PHY_AUX_SPD_1000:
232 phydev->speed = SPEED_1000;
233 break;
234 case PHY_AUX_SPD_2500:
235 phydev->speed = SPEED_2500;
236 break;
237 }
238
239 phydev->duplex = DUPLEX_FULL;
240 phydev->rate_matching = RATE_MATCH_PAUSE;
241 }
242
243 return 0;
244 }
245
mt798x_2p5ge_phy_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)246 static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
247 phy_interface_t iface)
248 {
249 return RATE_MATCH_PAUSE;
250 }
251
mt798x_2p5ge_phy_probe(struct phy_device * phydev)252 static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
253 {
254 struct pinctrl *pinctrl;
255 int ret;
256
257 switch (phydev->drv->phy_id) {
258 case MTK_2P5GPHY_ID_MT7988:
259 /* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD.
260 * Set the rest by this driver since PCS/AN/VEND1/VEND2 MDIO
261 * manageable devices actually exist.
262 */
263 phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
264 MDIO_DEVS_AN |
265 MDIO_DEVS_VEND1 |
266 MDIO_DEVS_VEND2;
267 break;
268 default:
269 return -EINVAL;
270 }
271
272 ret = mt798x_2p5ge_phy_load_fw(phydev);
273 if (ret < 0)
274 return ret;
275
276 /* Setup LED */
277 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
278 MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
279 MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
280 MTK_PHY_LED_ON_LINK2500);
281 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
282 MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
283
284 /* Switch pinctrl after setting polarity to avoid bogus blinking */
285 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
286 if (IS_ERR(pinctrl))
287 dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
288
289 return 0;
290 }
291
292 static struct phy_driver mtk_2p5gephy_driver[] = {
293 {
294 PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988),
295 .name = "MediaTek MT7988 2.5GbE PHY",
296 .probe = mt798x_2p5ge_phy_probe,
297 .config_init = mt798x_2p5ge_phy_config_init,
298 .config_aneg = mt798x_2p5ge_phy_config_aneg,
299 .get_features = mt798x_2p5ge_phy_get_features,
300 .read_status = mt798x_2p5ge_phy_read_status,
301 .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching,
302 .suspend = genphy_suspend,
303 .resume = genphy_resume,
304 .read_page = mtk_phy_read_page,
305 .write_page = mtk_phy_write_page,
306 },
307 };
308
309 module_phy_driver(mtk_2p5gephy_driver);
310
311 static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
312 { PHY_ID_MATCH_VENDOR(0x00339c00) },
313 { }
314 };
315
316 MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
317 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
318 MODULE_LICENSE("GPL");
319
320 MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
321 MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW);
322