1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/debugfs.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/platform_device.h>
12
13 #include <linux/soc/qcom/ubwc.h>
14
15 static const struct qcom_ubwc_cfg_data msm8937_data = {
16 .ubwc_enc_version = UBWC_1_0,
17 .ubwc_dec_version = UBWC_1_0,
18 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
19 UBWC_SWIZZLE_ENABLE_LVL2 |
20 UBWC_SWIZZLE_ENABLE_LVL3,
21 .highest_bank_bit = 14,
22 };
23
24 static const struct qcom_ubwc_cfg_data msm8998_data = {
25 .ubwc_enc_version = UBWC_1_0,
26 .ubwc_dec_version = UBWC_1_0,
27 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
28 UBWC_SWIZZLE_ENABLE_LVL2 |
29 UBWC_SWIZZLE_ENABLE_LVL3,
30 .highest_bank_bit = 15,
31 };
32
33 static const struct qcom_ubwc_cfg_data qcm2290_data = {
34 /* no UBWC */
35 .highest_bank_bit = 15,
36 };
37
38 static const struct qcom_ubwc_cfg_data sa8775p_data = {
39 .ubwc_enc_version = UBWC_4_0,
40 .ubwc_dec_version = UBWC_4_0,
41 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
42 .ubwc_bank_spread = true,
43 .highest_bank_bit = 13,
44 .macrotile_mode = true,
45 };
46
47 static const struct qcom_ubwc_cfg_data sar2130p_data = {
48 .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
49 .ubwc_dec_version = UBWC_4_3,
50 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
51 UBWC_SWIZZLE_ENABLE_LVL3,
52 .ubwc_bank_spread = true,
53 .highest_bank_bit = 13,
54 .macrotile_mode = true,
55 };
56
57 static const struct qcom_ubwc_cfg_data sc7180_data = {
58 .ubwc_enc_version = UBWC_2_0,
59 .ubwc_dec_version = UBWC_2_0,
60 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
61 UBWC_SWIZZLE_ENABLE_LVL3,
62 .ubwc_bank_spread = true,
63 .highest_bank_bit = 14,
64 };
65
66 static const struct qcom_ubwc_cfg_data sc7280_data = {
67 .ubwc_enc_version = UBWC_3_0,
68 .ubwc_dec_version = UBWC_4_0,
69 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
70 UBWC_SWIZZLE_ENABLE_LVL3,
71 .ubwc_bank_spread = true,
72 .highest_bank_bit = 14,
73 .macrotile_mode = true,
74 };
75
76 static const struct qcom_ubwc_cfg_data sc8180x_data = {
77 .ubwc_enc_version = UBWC_3_0,
78 .ubwc_dec_version = UBWC_3_0,
79 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
80 UBWC_SWIZZLE_ENABLE_LVL3,
81 .highest_bank_bit = 16,
82 .macrotile_mode = true,
83 };
84
85 static const struct qcom_ubwc_cfg_data sc8280xp_data = {
86 .ubwc_enc_version = UBWC_4_0,
87 .ubwc_dec_version = UBWC_4_0,
88 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
89 UBWC_SWIZZLE_ENABLE_LVL3,
90 .ubwc_bank_spread = true,
91 .highest_bank_bit = 16,
92 .macrotile_mode = true,
93 };
94
95 static const struct qcom_ubwc_cfg_data sdm670_data = {
96 .ubwc_enc_version = UBWC_2_0,
97 .ubwc_dec_version = UBWC_2_0,
98 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
99 UBWC_SWIZZLE_ENABLE_LVL3,
100 .highest_bank_bit = 14,
101 };
102
103 static const struct qcom_ubwc_cfg_data sdm845_data = {
104 .ubwc_enc_version = UBWC_2_0,
105 .ubwc_dec_version = UBWC_2_0,
106 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
107 UBWC_SWIZZLE_ENABLE_LVL3,
108 .highest_bank_bit = 15,
109 };
110
111 static const struct qcom_ubwc_cfg_data sm6115_data = {
112 .ubwc_enc_version = UBWC_1_0,
113 .ubwc_dec_version = UBWC_2_0,
114 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
115 UBWC_SWIZZLE_ENABLE_LVL2 |
116 UBWC_SWIZZLE_ENABLE_LVL3,
117 .ubwc_bank_spread = true,
118 .highest_bank_bit = 14,
119 };
120
121 static const struct qcom_ubwc_cfg_data sm6125_data = {
122 .ubwc_enc_version = UBWC_1_0,
123 .ubwc_dec_version = UBWC_3_0,
124 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
125 UBWC_SWIZZLE_ENABLE_LVL2 |
126 UBWC_SWIZZLE_ENABLE_LVL3,
127 .highest_bank_bit = 14,
128 };
129
130 static const struct qcom_ubwc_cfg_data sm6150_data = {
131 .ubwc_enc_version = UBWC_2_0,
132 .ubwc_dec_version = UBWC_2_0,
133 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
134 UBWC_SWIZZLE_ENABLE_LVL3,
135 .highest_bank_bit = 14,
136 };
137
138 static const struct qcom_ubwc_cfg_data sm6350_data = {
139 .ubwc_enc_version = UBWC_2_0,
140 .ubwc_dec_version = UBWC_2_0,
141 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
142 UBWC_SWIZZLE_ENABLE_LVL3,
143 .ubwc_bank_spread = true,
144 .highest_bank_bit = 14,
145 };
146
147 static const struct qcom_ubwc_cfg_data sm7150_data = {
148 .ubwc_enc_version = UBWC_2_0,
149 .ubwc_dec_version = UBWC_2_0,
150 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
151 UBWC_SWIZZLE_ENABLE_LVL3,
152 .highest_bank_bit = 14,
153 };
154
155 static const struct qcom_ubwc_cfg_data sm8150_data = {
156 .ubwc_enc_version = UBWC_3_0,
157 .ubwc_dec_version = UBWC_3_0,
158 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
159 UBWC_SWIZZLE_ENABLE_LVL3,
160 .highest_bank_bit = 15,
161 };
162
163 static const struct qcom_ubwc_cfg_data sm8250_data = {
164 .ubwc_enc_version = UBWC_4_0,
165 .ubwc_dec_version = UBWC_4_0,
166 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
167 UBWC_SWIZZLE_ENABLE_LVL3,
168 .ubwc_bank_spread = true,
169 /* TODO: highest_bank_bit = 15 for LP_DDR4 */
170 .highest_bank_bit = 16,
171 .macrotile_mode = true,
172 };
173
174 static const struct qcom_ubwc_cfg_data sm8350_data = {
175 .ubwc_enc_version = UBWC_4_0,
176 .ubwc_dec_version = UBWC_4_0,
177 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
178 UBWC_SWIZZLE_ENABLE_LVL3,
179 .ubwc_bank_spread = true,
180 /* TODO: highest_bank_bit = 15 for LP_DDR4 */
181 .highest_bank_bit = 16,
182 .macrotile_mode = true,
183 };
184
185 static const struct qcom_ubwc_cfg_data sm8550_data = {
186 .ubwc_enc_version = UBWC_4_0,
187 .ubwc_dec_version = UBWC_4_3,
188 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
189 UBWC_SWIZZLE_ENABLE_LVL3,
190 .ubwc_bank_spread = true,
191 /* TODO: highest_bank_bit = 15 for LP_DDR4 */
192 .highest_bank_bit = 16,
193 .macrotile_mode = true,
194 };
195
196 static const struct qcom_ubwc_cfg_data sm8750_data = {
197 .ubwc_enc_version = UBWC_5_0,
198 .ubwc_dec_version = UBWC_5_0,
199 .ubwc_swizzle = 6,
200 .ubwc_bank_spread = true,
201 /* TODO: highest_bank_bit = 15 for LP_DDR4 */
202 .highest_bank_bit = 16,
203 .macrotile_mode = true,
204 };
205
206 static const struct qcom_ubwc_cfg_data x1e80100_data = {
207 .ubwc_enc_version = UBWC_4_0,
208 .ubwc_dec_version = UBWC_4_3,
209 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
210 UBWC_SWIZZLE_ENABLE_LVL3,
211 .ubwc_bank_spread = true,
212 /* TODO: highest_bank_bit = 15 for LP_DDR4 */
213 .highest_bank_bit = 16,
214 .macrotile_mode = true,
215 };
216
217 static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
218 { .compatible = "qcom,apq8096", .data = &msm8998_data },
219 { .compatible = "qcom,msm8917", .data = &msm8937_data },
220 { .compatible = "qcom,msm8937", .data = &msm8937_data },
221 { .compatible = "qcom,msm8953", .data = &msm8937_data },
222 { .compatible = "qcom,msm8956", .data = &msm8937_data },
223 { .compatible = "qcom,msm8976", .data = &msm8937_data },
224 { .compatible = "qcom,msm8996", .data = &msm8998_data },
225 { .compatible = "qcom,msm8998", .data = &msm8998_data },
226 { .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
227 { .compatible = "qcom,qcm6490", .data = &sc7280_data, },
228 { .compatible = "qcom,sa8155p", .data = &sm8150_data, },
229 { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
230 { .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
231 { .compatible = "qcom,sar2130p", .data = &sar2130p_data },
232 { .compatible = "qcom,sc7180", .data = &sc7180_data },
233 { .compatible = "qcom,sc7280", .data = &sc7280_data, },
234 { .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
235 { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
236 { .compatible = "qcom,sdm630", .data = &msm8937_data },
237 { .compatible = "qcom,sdm636", .data = &msm8937_data },
238 { .compatible = "qcom,sdm660", .data = &msm8937_data },
239 { .compatible = "qcom,sdm670", .data = &sdm670_data, },
240 { .compatible = "qcom,sdm845", .data = &sdm845_data, },
241 { .compatible = "qcom,sm4250", .data = &sm6115_data, },
242 { .compatible = "qcom,sm6115", .data = &sm6115_data, },
243 { .compatible = "qcom,sm6125", .data = &sm6125_data, },
244 { .compatible = "qcom,sm6150", .data = &sm6150_data, },
245 { .compatible = "qcom,sm6350", .data = &sm6350_data, },
246 { .compatible = "qcom,sm6375", .data = &sm6350_data, },
247 { .compatible = "qcom,sm7125", .data = &sc7180_data },
248 { .compatible = "qcom,sm7150", .data = &sm7150_data, },
249 { .compatible = "qcom,sm8150", .data = &sm8150_data, },
250 { .compatible = "qcom,sm8250", .data = &sm8250_data, },
251 { .compatible = "qcom,sm8350", .data = &sm8350_data, },
252 { .compatible = "qcom,sm8450", .data = &sm8350_data, },
253 { .compatible = "qcom,sm8550", .data = &sm8550_data, },
254 { .compatible = "qcom,sm8650", .data = &sm8550_data, },
255 { .compatible = "qcom,sm8750", .data = &sm8750_data, },
256 { .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
257 { .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
258 { }
259 };
260
qcom_ubwc_config_get_data(void)261 const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
262 {
263 const struct of_device_id *match;
264 struct device_node *root;
265
266 root = of_find_node_by_path("/");
267 if (!root)
268 return ERR_PTR(-ENODEV);
269
270 match = of_match_node(qcom_ubwc_configs, root);
271 of_node_put(root);
272 if (!match) {
273 pr_err("Couldn't find UBWC config data for this platform!\n");
274 return ERR_PTR(-EINVAL);
275 }
276
277 return match->data;
278 }
279 EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data);
280
281 MODULE_LICENSE("GPL");
282 MODULE_DESCRIPTION("UBWC config database for QTI SoCs");
283