1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
4 *
5 * Copyright (C) 2018 Jacob Feder
6 *
7 * Authors: Jacob Feder <jacobsfeder@gmail.com>
8 *
9 * See Xilinx PG080 document for IP details
10 */
11
12 /* ----------------------------
13 * includes
14 * ----------------------------
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/wait.h>
21 #include <linux/mutex.h>
22 #include <linux/device.h>
23 #include <linux/cdev.h>
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27 #include <linux/io.h>
28 #include <linux/moduleparam.h>
29 #include <linux/interrupt.h>
30 #include <linux/param.h>
31 #include <linux/fs.h>
32 #include <linux/types.h>
33 #include <linux/uaccess.h>
34 #include <linux/jiffies.h>
35 #include <linux/miscdevice.h>
36 #include <linux/debugfs.h>
37
38 /* ----------------------------
39 * driver parameters
40 * ----------------------------
41 */
42
43 #define DRIVER_NAME "axis_fifo"
44
45 #define READ_BUF_SIZE 128U /* read buffer length in words */
46 #define WRITE_BUF_SIZE 128U /* write buffer length in words */
47
48 #define AXIS_FIFO_DEBUG_REG_NAME_MAX_LEN 4
49
50 /* ----------------------------
51 * IP register offsets
52 * ----------------------------
53 */
54
55 #define XLLF_ISR_OFFSET 0x00000000 /* Interrupt Status */
56 #define XLLF_IER_OFFSET 0x00000004 /* Interrupt Enable */
57
58 #define XLLF_TDFR_OFFSET 0x00000008 /* Transmit Reset */
59 #define XLLF_TDFV_OFFSET 0x0000000c /* Transmit Vacancy */
60 #define XLLF_TDFD_OFFSET 0x00000010 /* Transmit Data */
61 #define XLLF_TLR_OFFSET 0x00000014 /* Transmit Length */
62
63 #define XLLF_RDFR_OFFSET 0x00000018 /* Receive Reset */
64 #define XLLF_RDFO_OFFSET 0x0000001c /* Receive Occupancy */
65 #define XLLF_RDFD_OFFSET 0x00000020 /* Receive Data */
66 #define XLLF_RLR_OFFSET 0x00000024 /* Receive Length */
67 #define XLLF_SRR_OFFSET 0x00000028 /* Local Link Reset */
68 #define XLLF_TDR_OFFSET 0x0000002C /* Transmit Destination */
69 #define XLLF_RDR_OFFSET 0x00000030 /* Receive Destination */
70
71 /* ----------------------------
72 * reset register masks
73 * ----------------------------
74 */
75
76 #define XLLF_RDFR_RESET_MASK 0x000000a5 /* receive reset value */
77 #define XLLF_TDFR_RESET_MASK 0x000000a5 /* Transmit reset value */
78 #define XLLF_SRR_RESET_MASK 0x000000a5 /* Local Link reset value */
79
80 /* ----------------------------
81 * interrupt masks
82 * ----------------------------
83 */
84
85 #define XLLF_INT_RPURE_MASK 0x80000000 /* Receive under-read */
86 #define XLLF_INT_RPORE_MASK 0x40000000 /* Receive over-read */
87 #define XLLF_INT_RPUE_MASK 0x20000000 /* Receive underrun (empty) */
88 #define XLLF_INT_TPOE_MASK 0x10000000 /* Transmit overrun */
89 #define XLLF_INT_TC_MASK 0x08000000 /* Transmit complete */
90 #define XLLF_INT_RC_MASK 0x04000000 /* Receive complete */
91 #define XLLF_INT_TSE_MASK 0x02000000 /* Transmit length mismatch */
92 #define XLLF_INT_TRC_MASK 0x01000000 /* Transmit reset complete */
93 #define XLLF_INT_RRC_MASK 0x00800000 /* Receive reset complete */
94 #define XLLF_INT_TFPF_MASK 0x00400000 /* Tx FIFO Programmable Full */
95 #define XLLF_INT_TFPE_MASK 0x00200000 /* Tx FIFO Programmable Empty */
96 #define XLLF_INT_RFPF_MASK 0x00100000 /* Rx FIFO Programmable Full */
97 #define XLLF_INT_RFPE_MASK 0x00080000 /* Rx FIFO Programmable Empty */
98 #define XLLF_INT_ALL_MASK 0xfff80000 /* All the ints */
99 #define XLLF_INT_ERROR_MASK 0xf2000000 /* Error status ints */
100 #define XLLF_INT_RXERROR_MASK 0xe0000000 /* Receive Error status ints */
101 #define XLLF_INT_TXERROR_MASK 0x12000000 /* Transmit Error status ints */
102
103 /* ----------------------------
104 * globals
105 * ----------------------------
106 */
107 static long read_timeout = 1000; /* ms to wait before read() times out */
108 static long write_timeout = 1000; /* ms to wait before write() times out */
109
110 /* ----------------------------
111 * module command-line arguments
112 * ----------------------------
113 */
114
115 module_param(read_timeout, long, 0444);
116 MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out; set to -1 for no timeout");
117 module_param(write_timeout, long, 0444);
118 MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing out; set to -1 for no timeout");
119
120 /* ----------------------------
121 * types
122 * ----------------------------
123 */
124
125 struct axis_fifo {
126 int irq; /* interrupt */
127 void __iomem *base_addr; /* kernel space memory */
128
129 unsigned int rx_fifo_depth; /* max words in the receive fifo */
130 unsigned int tx_fifo_depth; /* max words in the transmit fifo */
131 int has_rx_fifo; /* whether the IP has the rx fifo enabled */
132 int has_tx_fifo; /* whether the IP has the tx fifo enabled */
133
134 wait_queue_head_t read_queue; /* wait queue for asynchronos read */
135 struct mutex read_lock; /* lock for reading */
136 wait_queue_head_t write_queue; /* wait queue for asynchronos write */
137 struct mutex write_lock; /* lock for writing */
138 unsigned int write_flags; /* write file flags */
139 unsigned int read_flags; /* read file flags */
140
141 struct device *dt_device; /* device created from the device tree */
142 struct miscdevice miscdev;
143
144 struct dentry *debugfs_dir;
145 };
146
147 struct axis_fifo_debug_reg {
148 const char * const name;
149 unsigned int offset;
150 };
151
152 /* ----------------------------
153 * implementation
154 * ----------------------------
155 */
156
reset_ip_core(struct axis_fifo * fifo)157 static void reset_ip_core(struct axis_fifo *fifo)
158 {
159 iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET);
160 iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET);
161 iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET);
162 iowrite32(XLLF_INT_TC_MASK | XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK |
163 XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK |
164 XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK,
165 fifo->base_addr + XLLF_IER_OFFSET);
166 iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET);
167 }
168
169 /**
170 * axis_fifo_read() - Read a packet from AXIS-FIFO character device.
171 * @f: Open file.
172 * @buf: User space buffer to read to.
173 * @len: User space buffer length.
174 * @off: Buffer offset.
175 *
176 * As defined by the device's documentation, we need to check the device's
177 * occupancy before reading the length register and then the data. All these
178 * operations must be executed atomically, in order and one after the other
179 * without missing any.
180 *
181 * Returns the number of bytes read from the device or negative error code
182 * on failure.
183 */
axis_fifo_read(struct file * f,char __user * buf,size_t len,loff_t * off)184 static ssize_t axis_fifo_read(struct file *f, char __user *buf,
185 size_t len, loff_t *off)
186 {
187 struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
188 size_t bytes_available;
189 unsigned int words_available;
190 unsigned int copied;
191 unsigned int copy;
192 unsigned int i;
193 int ret;
194 u32 tmp_buf[READ_BUF_SIZE];
195
196 if (fifo->read_flags & O_NONBLOCK) {
197 /*
198 * Device opened in non-blocking mode. Try to lock it and then
199 * check if any packet is available.
200 */
201 if (!mutex_trylock(&fifo->read_lock))
202 return -EAGAIN;
203
204 if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) {
205 ret = -EAGAIN;
206 goto end_unlock;
207 }
208 } else {
209 /* opened in blocking mode
210 * wait for a packet available interrupt (or timeout)
211 * if nothing is currently available
212 */
213 mutex_lock(&fifo->read_lock);
214 ret = wait_event_interruptible_timeout(fifo->read_queue,
215 ioread32(fifo->base_addr + XLLF_RDFO_OFFSET),
216 read_timeout);
217
218 if (ret <= 0) {
219 if (ret == 0) {
220 ret = -EAGAIN;
221 } else if (ret != -ERESTARTSYS) {
222 dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in read (ret=%i)\n",
223 ret);
224 }
225
226 goto end_unlock;
227 }
228 }
229
230 bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET);
231 if (!bytes_available) {
232 dev_err(fifo->dt_device, "received a packet of length 0\n");
233 ret = -EIO;
234 goto end_unlock;
235 }
236
237 if (bytes_available > len) {
238 dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu)\n",
239 bytes_available, len);
240 ret = -EINVAL;
241 goto end_unlock;
242 }
243
244 if (bytes_available % sizeof(u32)) {
245 /* this probably can't happen unless IP
246 * registers were previously mishandled
247 */
248 dev_err(fifo->dt_device, "received a packet that isn't word-aligned\n");
249 ret = -EIO;
250 goto end_unlock;
251 }
252
253 words_available = bytes_available / sizeof(u32);
254
255 /* read data into an intermediate buffer, copying the contents
256 * to userspace when the buffer is full
257 */
258 copied = 0;
259 while (words_available > 0) {
260 copy = min(words_available, READ_BUF_SIZE);
261
262 for (i = 0; i < copy; i++) {
263 tmp_buf[i] = ioread32(fifo->base_addr +
264 XLLF_RDFD_OFFSET);
265 }
266
267 if (copy_to_user(buf + copied * sizeof(u32), tmp_buf,
268 copy * sizeof(u32))) {
269 ret = -EFAULT;
270 goto end_unlock;
271 }
272
273 copied += copy;
274 words_available -= copy;
275 }
276
277 ret = bytes_available;
278
279 end_unlock:
280 mutex_unlock(&fifo->read_lock);
281
282 return ret;
283 }
284
285 /**
286 * axis_fifo_write() - Write buffer to AXIS-FIFO character device.
287 * @f: Open file.
288 * @buf: User space buffer to write to the device.
289 * @len: User space buffer length.
290 * @off: Buffer offset.
291 *
292 * As defined by the device's documentation, we need to write to the device's
293 * data buffer then to the device's packet length register atomically. Also,
294 * we need to lock before checking if the device has available space to avoid
295 * any concurrency issue.
296 *
297 * Returns the number of bytes written to the device or negative error code
298 * on failure.
299 */
axis_fifo_write(struct file * f,const char __user * buf,size_t len,loff_t * off)300 static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
301 size_t len, loff_t *off)
302 {
303 struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
304 unsigned int words_to_write;
305 unsigned int copied;
306 unsigned int copy;
307 unsigned int i;
308 int ret;
309 u32 tmp_buf[WRITE_BUF_SIZE];
310
311 if (len % sizeof(u32)) {
312 dev_err(fifo->dt_device,
313 "tried to send a packet that isn't word-aligned\n");
314 return -EINVAL;
315 }
316
317 words_to_write = len / sizeof(u32);
318
319 if (!words_to_write) {
320 dev_err(fifo->dt_device,
321 "tried to send a packet of length 0\n");
322 return -EINVAL;
323 }
324
325 if (words_to_write > fifo->tx_fifo_depth) {
326 dev_err(fifo->dt_device, "tried to write more words [%u] than slots in the fifo buffer [%u]\n",
327 words_to_write, fifo->tx_fifo_depth);
328 return -EINVAL;
329 }
330
331 if (fifo->write_flags & O_NONBLOCK) {
332 /*
333 * Device opened in non-blocking mode. Try to lock it and then
334 * check if there is any room to write the given buffer.
335 */
336 if (!mutex_trylock(&fifo->write_lock))
337 return -EAGAIN;
338
339 if (words_to_write > ioread32(fifo->base_addr +
340 XLLF_TDFV_OFFSET)) {
341 ret = -EAGAIN;
342 goto end_unlock;
343 }
344 } else {
345 /* opened in blocking mode */
346
347 /* wait for an interrupt (or timeout) if there isn't
348 * currently enough room in the fifo
349 */
350 mutex_lock(&fifo->write_lock);
351 ret = wait_event_interruptible_timeout(fifo->write_queue,
352 ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
353 >= words_to_write,
354 write_timeout);
355
356 if (ret <= 0) {
357 if (ret == 0) {
358 ret = -EAGAIN;
359 } else if (ret != -ERESTARTSYS) {
360 dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in write (ret=%i)\n",
361 ret);
362 }
363
364 goto end_unlock;
365 }
366 }
367
368 /* write data from an intermediate buffer into the fifo IP, refilling
369 * the buffer with userspace data as needed
370 */
371 copied = 0;
372 while (words_to_write > 0) {
373 copy = min(words_to_write, WRITE_BUF_SIZE);
374
375 if (copy_from_user(tmp_buf, buf + copied * sizeof(u32),
376 copy * sizeof(u32))) {
377 ret = -EFAULT;
378 goto end_unlock;
379 }
380
381 for (i = 0; i < copy; i++)
382 iowrite32(tmp_buf[i], fifo->base_addr +
383 XLLF_TDFD_OFFSET);
384
385 copied += copy;
386 words_to_write -= copy;
387 }
388
389 ret = copied * sizeof(u32);
390
391 /* write packet size to fifo */
392 iowrite32(ret, fifo->base_addr + XLLF_TLR_OFFSET);
393
394 end_unlock:
395 mutex_unlock(&fifo->write_lock);
396
397 return ret;
398 }
399
axis_fifo_irq(int irq,void * dw)400 static irqreturn_t axis_fifo_irq(int irq, void *dw)
401 {
402 struct axis_fifo *fifo = (struct axis_fifo *)dw;
403 unsigned int pending_interrupts;
404
405 do {
406 pending_interrupts = ioread32(fifo->base_addr +
407 XLLF_IER_OFFSET) &
408 ioread32(fifo->base_addr
409 + XLLF_ISR_OFFSET);
410 if (pending_interrupts & XLLF_INT_RC_MASK) {
411 /* packet received */
412
413 /* wake the reader process if it is waiting */
414 wake_up(&fifo->read_queue);
415
416 /* clear interrupt */
417 iowrite32(XLLF_INT_RC_MASK & XLLF_INT_ALL_MASK,
418 fifo->base_addr + XLLF_ISR_OFFSET);
419 } else if (pending_interrupts & XLLF_INT_TC_MASK) {
420 /* packet sent */
421
422 /* wake the writer process if it is waiting */
423 wake_up(&fifo->write_queue);
424
425 iowrite32(XLLF_INT_TC_MASK & XLLF_INT_ALL_MASK,
426 fifo->base_addr + XLLF_ISR_OFFSET);
427 } else if (pending_interrupts & XLLF_INT_TFPF_MASK) {
428 /* transmit fifo programmable full */
429
430 iowrite32(XLLF_INT_TFPF_MASK & XLLF_INT_ALL_MASK,
431 fifo->base_addr + XLLF_ISR_OFFSET);
432 } else if (pending_interrupts & XLLF_INT_TFPE_MASK) {
433 /* transmit fifo programmable empty */
434
435 iowrite32(XLLF_INT_TFPE_MASK & XLLF_INT_ALL_MASK,
436 fifo->base_addr + XLLF_ISR_OFFSET);
437 } else if (pending_interrupts & XLLF_INT_RFPF_MASK) {
438 /* receive fifo programmable full */
439
440 iowrite32(XLLF_INT_RFPF_MASK & XLLF_INT_ALL_MASK,
441 fifo->base_addr + XLLF_ISR_OFFSET);
442 } else if (pending_interrupts & XLLF_INT_RFPE_MASK) {
443 /* receive fifo programmable empty */
444
445 iowrite32(XLLF_INT_RFPE_MASK & XLLF_INT_ALL_MASK,
446 fifo->base_addr + XLLF_ISR_OFFSET);
447 } else if (pending_interrupts & XLLF_INT_TRC_MASK) {
448 /* transmit reset complete interrupt */
449
450 iowrite32(XLLF_INT_TRC_MASK & XLLF_INT_ALL_MASK,
451 fifo->base_addr + XLLF_ISR_OFFSET);
452 } else if (pending_interrupts & XLLF_INT_RRC_MASK) {
453 /* receive reset complete interrupt */
454
455 iowrite32(XLLF_INT_RRC_MASK & XLLF_INT_ALL_MASK,
456 fifo->base_addr + XLLF_ISR_OFFSET);
457 } else if (pending_interrupts & XLLF_INT_RPURE_MASK) {
458 /* receive fifo under-read error interrupt */
459 dev_err(fifo->dt_device,
460 "receive under-read interrupt\n");
461
462 iowrite32(XLLF_INT_RPURE_MASK & XLLF_INT_ALL_MASK,
463 fifo->base_addr + XLLF_ISR_OFFSET);
464 } else if (pending_interrupts & XLLF_INT_RPORE_MASK) {
465 /* receive over-read error interrupt */
466 dev_err(fifo->dt_device,
467 "receive over-read interrupt\n");
468
469 iowrite32(XLLF_INT_RPORE_MASK & XLLF_INT_ALL_MASK,
470 fifo->base_addr + XLLF_ISR_OFFSET);
471 } else if (pending_interrupts & XLLF_INT_RPUE_MASK) {
472 /* receive underrun error interrupt */
473 dev_err(fifo->dt_device,
474 "receive underrun error interrupt\n");
475
476 iowrite32(XLLF_INT_RPUE_MASK & XLLF_INT_ALL_MASK,
477 fifo->base_addr + XLLF_ISR_OFFSET);
478 } else if (pending_interrupts & XLLF_INT_TPOE_MASK) {
479 /* transmit overrun error interrupt */
480 dev_err(fifo->dt_device,
481 "transmit overrun error interrupt\n");
482
483 iowrite32(XLLF_INT_TPOE_MASK & XLLF_INT_ALL_MASK,
484 fifo->base_addr + XLLF_ISR_OFFSET);
485 } else if (pending_interrupts & XLLF_INT_TSE_MASK) {
486 /* transmit length mismatch error interrupt */
487 dev_err(fifo->dt_device,
488 "transmit length mismatch error interrupt\n");
489
490 iowrite32(XLLF_INT_TSE_MASK & XLLF_INT_ALL_MASK,
491 fifo->base_addr + XLLF_ISR_OFFSET);
492 } else if (pending_interrupts) {
493 /* unknown interrupt type */
494 dev_err(fifo->dt_device,
495 "unknown interrupt(s) 0x%x\n",
496 pending_interrupts);
497
498 iowrite32(XLLF_INT_ALL_MASK,
499 fifo->base_addr + XLLF_ISR_OFFSET);
500 }
501 } while (pending_interrupts);
502
503 return IRQ_HANDLED;
504 }
505
axis_fifo_open(struct inode * inod,struct file * f)506 static int axis_fifo_open(struct inode *inod, struct file *f)
507 {
508 struct axis_fifo *fifo = container_of(f->private_data,
509 struct axis_fifo, miscdev);
510 f->private_data = fifo;
511
512 if (((f->f_flags & O_ACCMODE) == O_WRONLY) ||
513 ((f->f_flags & O_ACCMODE) == O_RDWR)) {
514 if (fifo->has_tx_fifo) {
515 fifo->write_flags = f->f_flags;
516 } else {
517 dev_err(fifo->dt_device, "tried to open device for write but the transmit fifo is disabled\n");
518 return -EPERM;
519 }
520 }
521
522 if (((f->f_flags & O_ACCMODE) == O_RDONLY) ||
523 ((f->f_flags & O_ACCMODE) == O_RDWR)) {
524 if (fifo->has_rx_fifo) {
525 fifo->read_flags = f->f_flags;
526 } else {
527 dev_err(fifo->dt_device, "tried to open device for read but the receive fifo is disabled\n");
528 return -EPERM;
529 }
530 }
531
532 return 0;
533 }
534
axis_fifo_close(struct inode * inod,struct file * f)535 static int axis_fifo_close(struct inode *inod, struct file *f)
536 {
537 f->private_data = NULL;
538
539 return 0;
540 }
541
542 static const struct file_operations fops = {
543 .owner = THIS_MODULE,
544 .open = axis_fifo_open,
545 .release = axis_fifo_close,
546 .read = axis_fifo_read,
547 .write = axis_fifo_write
548 };
549
axis_fifo_debugfs_regs_show(struct seq_file * m,void * p)550 static int axis_fifo_debugfs_regs_show(struct seq_file *m, void *p)
551 {
552 static const struct axis_fifo_debug_reg regs[] = {
553 {"isr", XLLF_ISR_OFFSET},
554 {"ier", XLLF_IER_OFFSET},
555 {"tdfv", XLLF_TDFV_OFFSET},
556 {"rdfo", XLLF_RDFO_OFFSET},
557 { /* Sentinel */ },
558 };
559 const struct axis_fifo_debug_reg *reg;
560 struct axis_fifo *fifo = m->private;
561
562 for (reg = regs; reg->name; ++reg) {
563 u32 val = ioread32(fifo->base_addr + reg->offset);
564
565 seq_printf(m, "%*s: 0x%08x\n", AXIS_FIFO_DEBUG_REG_NAME_MAX_LEN,
566 reg->name, val);
567 }
568
569 return 0;
570 }
571 DEFINE_SHOW_ATTRIBUTE(axis_fifo_debugfs_regs);
572
axis_fifo_debugfs_init(struct axis_fifo * fifo)573 static void axis_fifo_debugfs_init(struct axis_fifo *fifo)
574 {
575 fifo->debugfs_dir = debugfs_create_dir(dev_name(fifo->dt_device), NULL);
576
577 debugfs_create_file("regs", 0444, fifo->debugfs_dir, fifo,
578 &axis_fifo_debugfs_regs_fops);
579 }
580
581 /* read named property from the device tree */
get_dts_property(struct axis_fifo * fifo,char * name,unsigned int * var)582 static int get_dts_property(struct axis_fifo *fifo,
583 char *name, unsigned int *var)
584 {
585 int rc;
586
587 rc = of_property_read_u32(fifo->dt_device->of_node, name, var);
588 if (rc) {
589 dev_err(fifo->dt_device, "couldn't read IP dts property '%s'",
590 name);
591 return rc;
592 }
593 dev_dbg(fifo->dt_device, "dts property '%s' = %u\n",
594 name, *var);
595
596 return 0;
597 }
598
axis_fifo_parse_dt(struct axis_fifo * fifo)599 static int axis_fifo_parse_dt(struct axis_fifo *fifo)
600 {
601 int ret;
602 unsigned int value;
603
604 ret = get_dts_property(fifo, "xlnx,axi-str-rxd-tdata-width", &value);
605 if (ret) {
606 dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n");
607 goto end;
608 } else if (value != 32) {
609 dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n");
610 ret = -EIO;
611 goto end;
612 }
613
614 ret = get_dts_property(fifo, "xlnx,axi-str-txd-tdata-width", &value);
615 if (ret) {
616 dev_err(fifo->dt_device, "missing xlnx,axi-str-txd-tdata-width property\n");
617 goto end;
618 } else if (value != 32) {
619 dev_err(fifo->dt_device, "xlnx,axi-str-txd-tdata-width only supports 32 bits\n");
620 ret = -EIO;
621 goto end;
622 }
623
624 ret = get_dts_property(fifo, "xlnx,rx-fifo-depth",
625 &fifo->rx_fifo_depth);
626 if (ret) {
627 dev_err(fifo->dt_device, "missing xlnx,rx-fifo-depth property\n");
628 ret = -EIO;
629 goto end;
630 }
631
632 ret = get_dts_property(fifo, "xlnx,tx-fifo-depth",
633 &fifo->tx_fifo_depth);
634 if (ret) {
635 dev_err(fifo->dt_device, "missing xlnx,tx-fifo-depth property\n");
636 ret = -EIO;
637 goto end;
638 }
639
640 ret = get_dts_property(fifo, "xlnx,use-rx-data", &fifo->has_rx_fifo);
641 if (ret) {
642 dev_err(fifo->dt_device, "missing xlnx,use-rx-data property\n");
643 ret = -EIO;
644 goto end;
645 }
646
647 ret = get_dts_property(fifo, "xlnx,use-tx-data", &fifo->has_tx_fifo);
648 if (ret) {
649 dev_err(fifo->dt_device, "missing xlnx,use-tx-data property\n");
650 ret = -EIO;
651 goto end;
652 }
653
654 end:
655 return ret;
656 }
657
axis_fifo_probe(struct platform_device * pdev)658 static int axis_fifo_probe(struct platform_device *pdev)
659 {
660 struct resource *r_mem; /* IO mem resources */
661 struct device *dev = &pdev->dev; /* OS device (from device tree) */
662 struct axis_fifo *fifo = NULL;
663 char *device_name;
664 int rc = 0; /* error return value */
665
666 /* ----------------------------
667 * init wrapper device
668 * ----------------------------
669 */
670
671 device_name = devm_kzalloc(dev, 32, GFP_KERNEL);
672 if (!device_name)
673 return -ENOMEM;
674
675 /* allocate device wrapper memory */
676 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
677 if (!fifo)
678 return -ENOMEM;
679
680 dev_set_drvdata(dev, fifo);
681 fifo->dt_device = dev;
682
683 init_waitqueue_head(&fifo->read_queue);
684 init_waitqueue_head(&fifo->write_queue);
685
686 mutex_init(&fifo->read_lock);
687 mutex_init(&fifo->write_lock);
688
689 /* ----------------------------
690 * init device memory space
691 * ----------------------------
692 */
693
694 /* get iospace for the device and request physical memory */
695 fifo->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
696 if (IS_ERR(fifo->base_addr)) {
697 rc = PTR_ERR(fifo->base_addr);
698 goto err_initial;
699 }
700
701 dev_dbg(fifo->dt_device, "remapped memory to 0x%p\n", fifo->base_addr);
702
703 /* create unique device name */
704 snprintf(device_name, 32, "%s_%pa", DRIVER_NAME, &r_mem->start);
705 dev_dbg(fifo->dt_device, "device name [%s]\n", device_name);
706
707 /* ----------------------------
708 * init IP
709 * ----------------------------
710 */
711
712 rc = axis_fifo_parse_dt(fifo);
713 if (rc)
714 goto err_initial;
715
716 reset_ip_core(fifo);
717
718 /* ----------------------------
719 * init device interrupts
720 * ----------------------------
721 */
722
723 /* get IRQ resource */
724 rc = platform_get_irq(pdev, 0);
725 if (rc < 0)
726 goto err_initial;
727
728 /* request IRQ */
729 fifo->irq = rc;
730 rc = devm_request_irq(fifo->dt_device, fifo->irq, &axis_fifo_irq, 0,
731 DRIVER_NAME, fifo);
732 if (rc) {
733 dev_err(fifo->dt_device, "couldn't allocate interrupt %i\n",
734 fifo->irq);
735 goto err_initial;
736 }
737
738 /* ----------------------------
739 * init char device
740 * ----------------------------
741 */
742
743 /* create character device */
744 fifo->miscdev.fops = &fops;
745 fifo->miscdev.minor = MISC_DYNAMIC_MINOR;
746 fifo->miscdev.name = device_name;
747 fifo->miscdev.parent = dev;
748 rc = misc_register(&fifo->miscdev);
749 if (rc < 0)
750 goto err_initial;
751
752 axis_fifo_debugfs_init(fifo);
753
754 return 0;
755
756 err_initial:
757 dev_set_drvdata(dev, NULL);
758 return rc;
759 }
760
axis_fifo_remove(struct platform_device * pdev)761 static void axis_fifo_remove(struct platform_device *pdev)
762 {
763 struct device *dev = &pdev->dev;
764 struct axis_fifo *fifo = dev_get_drvdata(dev);
765
766 debugfs_remove(fifo->debugfs_dir);
767 misc_deregister(&fifo->miscdev);
768 dev_set_drvdata(dev, NULL);
769 }
770
771 static const struct of_device_id axis_fifo_of_match[] = {
772 { .compatible = "xlnx,axi-fifo-mm-s-4.1", },
773 {},
774 };
775 MODULE_DEVICE_TABLE(of, axis_fifo_of_match);
776
777 static struct platform_driver axis_fifo_driver = {
778 .driver = {
779 .name = DRIVER_NAME,
780 .of_match_table = axis_fifo_of_match,
781 },
782 .probe = axis_fifo_probe,
783 .remove = axis_fifo_remove,
784 };
785
axis_fifo_init(void)786 static int __init axis_fifo_init(void)
787 {
788 if (read_timeout >= 0)
789 read_timeout = msecs_to_jiffies(read_timeout);
790 else
791 read_timeout = MAX_SCHEDULE_TIMEOUT;
792
793 if (write_timeout >= 0)
794 write_timeout = msecs_to_jiffies(write_timeout);
795 else
796 write_timeout = MAX_SCHEDULE_TIMEOUT;
797
798 pr_info("axis-fifo driver loaded with parameters read_timeout = %li, write_timeout = %li\n",
799 read_timeout, write_timeout);
800 return platform_driver_register(&axis_fifo_driver);
801 }
802
803 module_init(axis_fifo_init);
804
axis_fifo_exit(void)805 static void __exit axis_fifo_exit(void)
806 {
807 platform_driver_unregister(&axis_fifo_driver);
808 }
809
810 module_exit(axis_fifo_exit);
811
812 MODULE_LICENSE("GPL");
813 MODULE_AUTHOR("Jacob Feder <jacobsfeder@gmail.com>");
814 MODULE_DESCRIPTION("Xilinx AXI-Stream FIFO v4.1 IP core driver");
815