1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Register definitions for Cirrus Logic CS48L32 4 * 5 * Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef CS48L32_H 10 #define CS48L32_H 11 12 /* pll_id for snd_soc_component_set_pll() */ 13 #define CS48L32_FLL1_REFCLK 1 14 15 /* source for snd_soc_component_set_pll() */ 16 #define CS48L32_FLL_SRC_NONE -1 17 #define CS48L32_FLL_SRC_MCLK1 0 18 #define CS48L32_FLL_SRC_PDMCLK 5 19 #define CS48L32_FLL_SRC_ASP1_BCLK 8 20 #define CS48L32_FLL_SRC_ASP2_BCLK 9 21 #define CS48L32_FLL_SRC_ASP1_FSYNC 12 22 #define CS48L32_FLL_SRC_ASP2_FSYNC 13 23 24 /* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */ 25 #define CS48L32_CLK_SYSCLK_1 1 26 #define CS48L32_CLK_SYSCLK_2 2 27 #define CS48L32_CLK_SYSCLK_3 3 28 #define CS48L32_CLK_SYSCLK_4 4 29 #define CS48L32_CLK_DSPCLK 7 30 #define CS48L32_CLK_PDM_FLLCLK 13 31 32 /* source for snd_soc_component_set_sysclk() */ 33 #define CS48L32_CLK_SRC_MCLK1 0x0 34 #define CS48L32_CLK_SRC_FLL1 0x4 35 #define CS48L32_CLK_SRC_ASP1_BCLK 0x8 36 #define CS48L32_CLK_SRC_ASP2_BCLK 0x9 37 38 struct cs48l32 { 39 struct regmap *regmap; 40 struct device *dev; 41 struct gpio_desc *reset_gpio; 42 struct clk *mclk1; 43 struct regulator_bulk_data core_supplies[2]; 44 struct regulator *vdd_d; 45 int irq; 46 }; 47 #endif 48