Lines Matching refs:tmp
12 tmp .req x9 label
42 mov tmp, #(0b11<<20)
43 msr cpacr_el1, tmp
46 mrs tmp, sctlr_el1
47 orr tmp, tmp, #(1<<12) /* Enable icache */
48 orr tmp, tmp, #(1<<2) /* Enable dcache/ucache */
49 orr tmp, tmp, #(1<<3) /* Enable Stack Alignment Check EL1 */
50 orr tmp, tmp, #(1<<4) /* Enable Stack Alignment Check EL0 */
51 bic tmp, tmp, #(1<<1) /* Disable Alignment Checking for EL1 EL0 */
52 msr sctlr_el1, tmp
80 adrp tmp, arm64_boot_args
81 add tmp, tmp, :lo12:arm64_boot_args
82 stp x0, x1, [tmp], #16
83 stp x2, x3, [tmp]
86 adrp tmp, arm64_boot_el
87 str boot_el, [tmp, #:lo12:arm64_boot_el]
91 mov tmp, #0
93 str xzr, [page_table1, tmp, lsl #3]
94 add tmp, tmp, #1
95 cmp tmp, #MMU_KERNEL_PAGE_TABLE_ENTRIES_TOP
105 ldp size, tmp, [mmu_initial_mapping, #__MMU_INITIAL_MAPPING_SIZE_OFFSET]
107 tbzmask tmp, MMU_INITIAL_MAPPING_FLAG_DYNAMIC, .Lnot_dynamic
119 tbzmask tmp, MMU_INITIAL_MAPPING_FLAG_UNCACHED, .Lnot_uncached
125 tbzmask tmp, MMU_INITIAL_MAPPING_FLAG_DEVICE, .Lnot_device
147 ldr tmp, =__code_start
148 subs size, tmp, vaddr
153 ldr tmp, =__rodata_start
154 subs size, tmp, vaddr
157 ldr tmp, =__data_start
158 subs size, tmp, vaddr
161 ldr tmp, =_end
162 subs size, tmp, vaddr
173 orr tmp, vaddr, paddr
174 orr tmp, tmp, size
175 tst tmp, #(1 << MMU_KERNEL_PAGE_SIZE_SHIFT) - 1
203 lsr tmp, tmp2, idx_shift
204 lsl tmp, tmp, idx_shift
205 cmp tmp, tmp2
209 lsr tmp, size, idx_shift
210 cbz tmp, .Lmap_range_need_page_table
213 orr tmp, attr, #MMU_PTE_L3_DESCRIPTOR_PAGE
216 orr tmp, attr, #MMU_PTE_L012_DESCRIPTOR_BLOCK
220 orr tmp, tmp, paddr
221 str tmp, [page_table, idx, lsl #3]
224 mov tmp, #1
225 lsl tmp, tmp, idx_shift
226 add vaddr, vaddr, tmp
227 add paddr, paddr, tmp
228 subs size, size, tmp
249 ldr tmp, =.Lphys_offset /* virt */
250 sub phys_offset, tmp, phys_offset
253 calloc_bootmem_aligned new_page_table, tmp, tmp2, MMU_KERNEL_PAGE_SIZE_SHIFT, phys_offset
261 and tmp, new_page_table, #MMU_PTE_DESCRIPTOR_MASK
262 cmp tmp, #MMU_PTE_L012_DESCRIPTOR_TABLE
267 mov tmp, #~0
268 lsl tmp, tmp, idx_shift
269 bic tmp, vaddr, tmp
271 lsr idx, tmp, idx_shift
277 ldr tmp, =MMU_TCR_FLAGS_BASE
291 orr tmp, tmp, tmp2, lsl #32
293 str tmp, [tmp2, #:lo12:arm64_mmu_tcr_flags]
296 adrp tmp, page_tables_not_ready
297 add tmp, tmp, #:lo12:page_tables_not_ready
298 str wzr, [tmp]
302 adrp tmp, page_tables_not_ready
303 add tmp, tmp, #:lo12:page_tables_not_ready
305 ldr wtmp2, [tmp]
318 ldr tmp, =MMU_MAIR_VAL
319 msr mair_el1, tmp
324 adrp tmp, arm64_mmu_tcr_flags
325 ldr tmp, [tmp, #:lo12:arm64_mmu_tcr_flags]
326 orr tmp, tmp, #MMU_TCR_FLAGS_KERNEL
327 msr tcr_el1, tmp
337 ldr tmp, =trampoline_vbar
338 msr vbar_el1, tmp
342 mrs tmp, sctlr_el1
345 orr tmp, tmp, #0x1
353 msr sctlr_el1, tmp
372 ldr tmp, =__stack_end
373 mov sp, tmp
379 ldr tmp, =__post_prebss_bss_start
381 sub tmp2, tmp2, tmp
385 str xzr, [tmp], #8
390 adrp tmp, arm64_boot_args
391 add tmp, tmp, :lo12:arm64_boot_args
392 ldp x0, x1, [tmp], #16
393 ldp x2, x3, [tmp]
400 and tmp, cpuid, #0xff
401 cmp tmp, #(1 << SMP_CPU_CLUSTER_SHIFT)
404 orr cpuid, tmp, cpuid, LSR #(8 - SMP_CPU_CLUSTER_SHIFT)
410 ldr tmp, =__stack_end
413 sub sp, tmp, tmp2