1 /**
2 ******************************************************************************
3 * @file stm32f4xx_dfsdm.c
4 * @author MCD Application Team
5 * @version V1.8.1
6 * @date 27-January-2022
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of Digital Filter for Sigma Delta modulator
9 * (DFSDM) peripheral:
10 * + Initialization functions.
11 * + Configuration functions.
12 * + Interrupts and flags management functions.
13 *
14 * @verbatim
15 *
16 ================================================================================
17 ##### How to use this driver #####
18 ================================================================================
19 [..]
20
21 @endverbatim
22 ******************************************************************************
23 * @attention
24 *
25 * Copyright (c) 2016 STMicroelectronics.
26 * All rights reserved.
27 *
28 * This software is licensed under terms that can be found in the LICENSE file
29 * in the root directory of this software component.
30 * If no LICENSE file comes with this software, it is provided AS-IS.
31 *
32 ******************************************************************************
33 */
34
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32f4xx_dfsdm.h"
37 #include "stm32f4xx_rcc.h"
38
39 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @{
41 */
42
43 /** @defgroup DFSDM
44 * @brief DFSDM driver modules
45 * @{
46 */
47 #if defined(STM32F412xG) || defined(STM32F413_423xx)
48
49 /* External variables --------------------------------------------------------*/
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private defines -----------------------------------------------------------*/
52
53 #define CHCFGR_INIT_CLEAR_MASK (uint32_t) 0xFFFE0F10
54 /* Private macros ------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56 /* Private function prototypes -----------------------------------------------*/
57 /* Private functions ---------------------------------------------------------*/
58
59 /** @defgroup DFSDM_Private_Functions
60 * @{
61 */
62
63 /** @defgroup DFSDM_Group1 Initialization functions
64 * @brief Initialization functions
65 *
66 @verbatim
67 ===============================================================================
68 Initialization functions
69 ===============================================================================
70 This section provides functions allowing to:
71 - Deinitialize the DFSDM
72 - Initialize DFSDM serial channels transceiver
73 - Initialize DFSDM filter
74
75 @endverbatim
76 * @{
77 */
78
79 /**
80 * @brief Deinitializes the DFSDM peripheral registers to their default reset values.
81 * @param None.
82 * @retval None.
83 *
84 */
DFSDM_DeInit(void)85 void DFSDM_DeInit(void)
86 {
87 /* Enable LPTx reset state */
88 RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM1, ENABLE);
89 RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM1, DISABLE);
90 #if defined(STM32F413_423xx)
91 RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM2, ENABLE);
92 RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM2, DISABLE);
93 #endif /* STM32F413_423xx */
94 }
95
96 /**
97 * @brief Initializes the DFSDM serial channels transceiver according to the specified
98 * parameters in the DFSDM_TransceiverInit.
99 * @param DFSDM_Channelx: specifies the channel to be selected.
100 * This parameter can be one of the following values :
101 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
102 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
103 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
104 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
105 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
106 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
107 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
108 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
109 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
110 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
111 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
112 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
113 * @param DFSDM_TransceiverInitStruct: pointer to a DFSDM_TransceiverInitTypeDef structure
114 * that contains the configuration information for the specified channel.
115 * @retval None
116 * @note It is mandatory to disable the selected channel to use this function.
117 */
DFSDM_TransceiverInit(DFSDM_Channel_TypeDef * DFSDM_Channelx,DFSDM_TransceiverInitTypeDef * DFSDM_TransceiverInitStruct)118 void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct)
119 {
120 uint32_t tmpreg1 = 0;
121 uint32_t tmpreg2 = 0;
122
123 /* Check the parameters */
124 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
125 assert_param(IS_DFSDM_INTERFACE(DFSDM_TransceiverInitStruct->DFSDM_Interface));
126 assert_param(IS_DFSDM_Input_MODE(DFSDM_TransceiverInitStruct->DFSDM_Input));
127 assert_param(IS_DFSDM_Redirection_STATE(DFSDM_TransceiverInitStruct->DFSDM_Redirection));
128 assert_param(IS_DFSDM_PACK_MODE(DFSDM_TransceiverInitStruct->DFSDM_PackingMode));
129 assert_param(IS_DFSDM_CLOCK(DFSDM_TransceiverInitStruct->DFSDM_Clock));
130 assert_param(IS_DFSDM_DATA_RIGHT_BIT_SHIFT(DFSDM_TransceiverInitStruct->DFSDM_DataRightShift));
131 assert_param(IS_DFSDM_OFFSET(DFSDM_TransceiverInitStruct->DFSDM_Offset));
132 assert_param(IS_DFSDM_CLK_DETECTOR_STATE(DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector));
133 assert_param(IS_DFSDM_SC_DETECTOR_STATE(DFSDM_TransceiverInitStruct->DFSDM_ShortCircuitDetector));
134
135 /* Get the DFSDM Channelx CHCFGR1 value */
136 tmpreg1 = DFSDM_Channelx->CHCFGR1;
137
138 /* Clear SITP, CKABEN, SCDEN and SPICKSEL bits */
139 tmpreg1 &= CHCFGR_INIT_CLEAR_MASK;
140
141 /* Set or Reset SITP bits according to DFSDM_Interface value */
142 /* Set or Reset SPICKSEL bits according to DFSDM_Clock value */
143 /* Set or Reset DATMPX bits according to DFSDM_InputMode value */
144 /* Set or Reset CHINSEL bits according to DFSDM_Redirection value */
145 /* Set or Reset DATPACK bits according to DFSDM_PackingMode value */
146 /* Set or Reset CKABEN bit according to DFSDM_CLKAbsenceDetector value */
147 /* Set or Reset SCDEN bit according to DFSDM_ShortCircuitDetector value */
148 tmpreg1 |= (DFSDM_TransceiverInitStruct->DFSDM_Interface |
149 DFSDM_TransceiverInitStruct->DFSDM_Clock |
150 DFSDM_TransceiverInitStruct->DFSDM_Input |
151 DFSDM_TransceiverInitStruct->DFSDM_Redirection |
152 DFSDM_TransceiverInitStruct->DFSDM_PackingMode |
153 DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector |
154 DFSDM_TransceiverInitStruct->DFSDM_ShortCircuitDetector);
155
156 /* Write to DFSDM Channelx CHCFGR1R */
157 DFSDM_Channelx->CHCFGR1 = tmpreg1;
158
159 /* Get the DFSDM Channelx CHCFGR2 value */
160 tmpreg2 = DFSDM_Channelx->CHCFGR2;
161
162 /* Clear DTRBS and OFFSET bits */
163 tmpreg2 &= ~(DFSDM_CHCFGR2_DTRBS | DFSDM_CHCFGR2_OFFSET);
164
165 /* Set or Reset DTRBS bits according to DFSDM_DataRightShift value */
166 /* Set or Reset OFFSET bits according to DFSDM_Offset value */
167 tmpreg2 |= (((DFSDM_TransceiverInitStruct->DFSDM_DataRightShift) <<3 ) |
168 ((DFSDM_TransceiverInitStruct->DFSDM_Offset) <<8 ));
169
170 /* Write to DFSDM Channelx CHCFGR1R */
171 DFSDM_Channelx->CHCFGR2 = tmpreg2;
172 }
173
174 /**
175 * @brief Fills each DFSDM_TransceiverInitStruct member with its default value.
176 * @param DFSDM_TransceiverInitStruct : pointer to a DFSDM_TransceiverInitTypeDef structure
177 * which will be initialized.
178 * @retval None
179 */
DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef * DFSDM_TransceiverInitStruct)180 void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct)
181 {
182 /* SPI with rising edge to strobe data is selected as default serial interface */
183 DFSDM_TransceiverInitStruct->DFSDM_Interface = DFSDM_Interface_SPI_FallingEdge;
184
185 /* Clock coming from internal DFSDM_CKOUT output is selected as default serial clock */
186 DFSDM_TransceiverInitStruct->DFSDM_Clock = DFSDM_Clock_Internal;
187
188 /* No data right bit-shift is selected as default data right bit-shift */
189 DFSDM_TransceiverInitStruct->DFSDM_DataRightShift = 0x0;
190
191 /* No offset is selected as default offset */
192 DFSDM_TransceiverInitStruct->DFSDM_Offset = 0x0;
193
194 /* Clock Absence Detector is Enabled as default state */
195 DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector = DFSDM_CLKAbsenceDetector_Enable;
196 }
197
198 /**
199 * @brief Initializes the DFSDMx Filter according to the specified
200 * parameters in the DFSDM_FilterInitStruct.
201 * @param DFSDMx: specifies the filter to be selected :
202 * This parameter can be one of the following values :
203 * @arg DFSDM1_0 : DFSDM 1 Filter 0
204 * @arg DFSDM1_1 : DFSDM 1 Filter 1
205 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
206 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
207 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
208 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
209 * @param DFSDM_FilterInitStruct: pointer to a DFSDM_FilterInitTypeDef structure
210 * that contains the configuration information for the specified filter.
211 * @retval None
212 *
213 * @note It is mandatory to disable the selected filter to use this function.
214 */
DFSDM_FilterInit(DFSDM_Filter_TypeDef * DFSDMx,DFSDM_FilterInitTypeDef * DFSDM_FilterInitStruct)215 void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct)
216 {
217 uint32_t tmpreg1 = 0;
218
219 /* Check the parameters */
220 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
221 assert_param(IS_DFSDM_SINC_ORDER(DFSDM_FilterInitStruct->DFSDM_SincOrder));
222 assert_param(IS_DFSDM_SINC_OVRSMPL_RATIO(DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio));
223 assert_param(IS_DFSDM_INTG_OVRSMPL_RATIO(DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio));
224
225 /* Get the DFSDMx FCR value */
226 tmpreg1 = DFSDMx->FLTFCR;
227
228 /* Clear FORD, FOSR and IOSR bits */
229 tmpreg1 &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
230
231 /* Set or Reset FORD bits according to DFSDM_SincOrder value */
232 /* Set or Reset FOSR bits according to DFSDM_FilterOversamplingRatio value */
233 /* Set or Reset IOSR bits according to DFSDM_IntegratorOversamplingRatio value */
234 tmpreg1 |= (DFSDM_FilterInitStruct->DFSDM_SincOrder |
235 ((DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio -1) << 16) |
236 (DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio -1));
237
238 /* Write to DFSDMx FCR */
239 DFSDMx->FLTFCR = tmpreg1;
240 }
241
242 /**
243 * @brief Fills each DFSDM_FilterInitStruct member with its default value.
244 * @param DFSDM_FilterInitStruct: pointer to a DFSDM_FilterInitTypeDef structure
245 * which will be initialized.
246 * @retval None
247 */
DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef * DFSDM_FilterInitStruct)248 void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct)
249 {
250 /* Order = 3 is selected as default sinc order */
251 DFSDM_FilterInitStruct->DFSDM_SincOrder = DFSDM_SincOrder_Sinc3;
252
253 /* Ratio = 64 is selected as default oversampling ratio */
254 DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio = 64 ;
255
256 /* Ratio = 4 is selected as default integrator oversampling ratio */
257 DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio = 4;
258 }
259
260 /**
261 * @}
262 */
263
264 /** @defgroup DFSDM_Group2 Configuration functions
265 * @brief Configuration functions
266 *
267 @verbatim
268 ===============================================================================
269 Configuration functions
270 ===============================================================================
271 This section provides functions allowing to configure DFSDM:
272 - Enable/Disable (DFSDM peripheral, Channel, Filter)
273 - Configure Clock output
274 - Configure Injected/Regular channels for Conversion
275 - Configure short circuit detector
276 - Configure Analog watchdog filter
277
278 @endverbatim
279 * @{
280 */
281
282 #if defined(STM32F412xG)
283 /**
284 * @brief Enables or disables the DFSDM peripheral.
285 * @param NewState: new state of the DFSDM interface.
286 * This parameter can be: ENABLE or DISABLE.
287 * @retval None
288 */
DFSDM_Command(FunctionalState NewState)289 void DFSDM_Command(FunctionalState NewState)
290 {
291 /* Check the parameters */
292 assert_param(IS_FUNCTIONAL_STATE(NewState));
293
294 if (NewState != DISABLE)
295 {
296 /* Set the ENABLE bit */
297 DFSDM1_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
298 }
299 else
300 {
301 /* Reset the ENABLE bit */
302 DFSDM1_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
303 }
304 }
305 #endif /* STM32F412xG */
306
307 #if defined(STM32F413_423xx)
308 /**
309 * @brief Enables or disables the DFSDM peripheral.
310 * @param Instance: select the instance of DFSDM
311 * This parameter can be: 1 or 2.
312 * @param NewState: new state of the DFSDM interface.
313 * This parameter can be: ENABLE or DISABLE.
314 * @retval None
315 */
DFSDM_Cmd(uint32_t Instance,FunctionalState NewState)316 void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState)
317 {
318 /* Check the parameters */
319 assert_param(IS_FUNCTIONAL_STATE(NewState));
320
321 if(Instance == 1)
322 {
323 if (NewState != DISABLE)
324 {
325 /* Set the ENABLE bit */
326 DFSDM1_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
327 }
328 else
329 {
330 /* Reset the ENABLE bit */
331 DFSDM1_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
332 }
333 }
334 else /* DFSDM2 */
335 {
336 if (NewState != DISABLE)
337 {
338 /* Set the ENABLE bit */
339 DFSDM2_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
340 }
341 else
342 {
343 /* Reset the ENABLE bit */
344 DFSDM2_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
345 }
346 }
347 }
348 #endif /* STM32F413_423xx */
349 /**
350 * @brief Enables or disables the specified DFSDM serial channelx.
351 * @param DFSDM_Channelx: specifies the channel to be selected.
352 * This parameter can be one of the following values :
353 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
354 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
355 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
356 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
357 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
358 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
359 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
360 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
361 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
362 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
363 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
364 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
365 * @param NewState: new state of the DFSDM serial channelx .
366 * This parameter can be: ENABLE or DISABLE.
367 * @retval None
368 */
DFSDM_ChannelCmd(DFSDM_Channel_TypeDef * DFSDM_Channelx,FunctionalState NewState)369 void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState)
370 {
371 /* Check the parameters */
372 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
373 assert_param(IS_FUNCTIONAL_STATE(NewState));
374
375 if (NewState != DISABLE)
376 {
377 /* Set the ENABLE bit */
378 DFSDM_Channelx->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
379 }
380 else
381 {
382 /* Reset the ENABLE bit */
383 DFSDM_Channelx->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
384 }
385 }
386
387 /**
388 * @brief Enables or disables the specified DFSDMx Filter.
389 * @param DFSDMx: specifies the filter to be selected :
390 * This parameter can be one of the following values :
391 * @arg DFSDM1_0 : DFSDM 1 Filter 0
392 * @arg DFSDM1_1 : DFSDM 1 Filter 1
393 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
394 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
395 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
396 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
397 * @param NewState: new state of the selected DFSDM module.
398 * This parameter can be: ENABLE or DISABLE.
399 * @retval None
400 */
DFSDM_FilterCmd(DFSDM_Filter_TypeDef * DFSDMx,FunctionalState NewState)401 void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
402 {
403 /* Check the parameters */
404 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
405 assert_param(IS_FUNCTIONAL_STATE(NewState));
406
407 if (NewState != DISABLE)
408 {
409 /* Set the ENABLE bit */
410 DFSDMx->FLTCR1 |= DFSDM_FLTCR1_DFEN;
411 }
412 else
413 {
414 /* Reset the ENABLE bit */
415 DFSDMx->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
416 }
417 }
418
419 #if defined(STM32F412xG)
420 /**
421 * @brief Configures the Output serial clock divider.
422 * @param DFSDM_ClkOutDivision: Defines the divider for the output serial clock
423 * This parameter can be a value between 1 and 256.
424 * @retval None
425 * @note The output serial clock is stopped if the divider =1.
426 * By default the serial output clock is stopped.
427 */
DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision)428 void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision)
429 {
430 uint32_t tmpreg1 = 0;
431
432 /* Check the parameters */
433 assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
434
435 /* Get the DFSDM_Channel0 CHCFGR1 value */
436 tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
437
438 /* Clear the CKOUTDIV bits */
439 tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
440
441 /* Set or Reset the CKOUTDIV bits */
442 tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
443
444 /* Write to DFSDM Channel0 CHCFGR1 */
445 DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
446 }
447
448 /**
449 * @brief Configures the Output serial clock source.
450 * @param DFSDM_ClkOutSource: Defines the divider for the output serial clock
451 * This parameter can be a value of:
452 * @arg DFSDM_ClkOutSource_SysClock
453 * @arg DFSDM_ClkOutSource_AudioClock
454 * @retval None
455 */
DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource)456 void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource)
457 {
458 uint32_t tmpreg1 = 0;
459
460 /* Check the parameters */
461 assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
462
463 /* Get the DFSDM_Channel0 CHCFGR1 value */
464 tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
465
466 /* Clear the CKOUTSRC bit */
467 tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
468
469 /* Set or Reset the CKOUTSRC bit */
470 tmpreg1 |= DFSDM_ClkOutSource;
471
472 /* Write to DFSDM Channel0 CHCFGR1 */
473 DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
474 }
475 #endif /* STM32F412xG */
476 #if defined(STM32F413_423xx)
477 /**
478 * @brief Configures the Output serial clock divider.
479 * @param Instance: select the instance of DFSDM
480 * This parameter can be: 1 or 2.
481 * @param DFSDM_ClkOutDivision: Defines the divider for the output serial clock
482 * This parameter can be a value between 1 and 256.
483 * @retval None
484 * @note The output serial clock is stopped if the divider =1.
485 * By default the serial output clock is stopped.
486 */
DFSDM_ConfigClkOutputDivider(uint32_t Instance,uint32_t DFSDM_ClkOutDivision)487 void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision)
488 {
489 uint32_t tmpreg1 = 0;
490
491 if(Instance == 1)
492 {
493 /* Check the parameters */
494 assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
495
496 /* Get the DFSDM_Channel0 CHCFGR1 value */
497 tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
498
499 /* Clear the CKOUTDIV bits */
500 tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
501
502 /* Set or Reset the CKOUTDIV bits */
503 tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
504
505 /* Write to DFSDM Channel0 CHCFGR1 */
506 DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
507 }
508 else /* DFSDM2 */
509 {
510 /* Check the parameters */
511 assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
512
513 /* Get the DFSDM_Channel0 CHCFGR1 value */
514 tmpreg1 = DFSDM2_Channel0 -> CHCFGR1;
515
516 /* Clear the CKOUTDIV bits */
517 tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
518
519 /* Set or Reset the CKOUTDIV bits */
520 tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
521
522 /* Write to DFSDM Channel0 CHCFGR1 */
523 DFSDM2_Channel0 -> CHCFGR1 = tmpreg1;
524 }
525 }
526
527 /**
528 * @brief Configures the Output serial clock source.
529 * @param Instance: select the instance of DFSDM
530 * This parameter can be: 1 or 2.
531 * @param DFSDM_ClkOutSource: Defines the divider for the output serial clock
532 * This parameter can be a value of:
533 * @arg DFSDM_ClkOutSource_SysClock
534 * @arg DFSDM_ClkOutSource_AudioClock
535 * @retval None
536 */
DFSDM_ConfigClkOutputSource(uint32_t Instance,uint32_t DFSDM_ClkOutSource)537 void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource)
538 {
539 uint32_t tmpreg1 = 0;
540
541 if(Instance == 1)
542 {
543 /* Check the parameters */
544 assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
545
546 /* Get the DFSDM_Channel0 CHCFGR1 value */
547 tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
548
549 /* Clear the CKOUTSRC bit */
550 tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
551
552 /* Set or Reset the CKOUTSRC bit */
553 tmpreg1 |= DFSDM_ClkOutSource;
554
555 /* Write to DFSDM Channel0 CHCFGR1 */
556 DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
557 }
558 else /* DFSDM2 */
559 {
560 /* Check the parameters */
561 assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
562
563 /* Get the DFSDM_Channel0 CHCFGR1 value */
564 tmpreg1 = DFSDM2_Channel0 -> CHCFGR1;
565
566 /* Clear the CKOUTSRC bit */
567 tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
568
569 /* Set or Reset the CKOUTSRC bit */
570 tmpreg1 |= DFSDM_ClkOutSource;
571
572 /* Write to DFSDM Channel0 CHCFGR1 */
573 DFSDM2_Channel0 -> CHCFGR1 = tmpreg1;
574 }
575 }
576 #endif /* STM32F413_423xx */
577 /**
578 * @brief Enables or disables the specified Break_i siganl to the specified DFSDM_Channelx.
579 * @param DFSDM_Channelx: specifies the channel to be selected.
580 * This parameter can be one of the following values :
581 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
582 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
583 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
584 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
585 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
586 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
587 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
588 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
589 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
590 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
591 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
592 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
593 * @param DFSDM_SCDBreak_i: where i can be a value from 0 to 3 to select the specified Break signal.
594 * @param NewState: new state of the selected DFSDM_SCDBreak_i.
595 * This parameter can be: ENABLE or DISABLE.
596 * @retval None
597 */
DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef * DFSDM_Channelx,uint32_t DFSDM_SCDBreak_i,FunctionalState NewState)598 void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState)
599 {
600 /* Check the parameters */
601 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
602 assert_param(IS_DFSDM_SCD_BREAK_SIGNAL(DFSDM_SCDBreak_i));
603 assert_param(IS_FUNCTIONAL_STATE(NewState));
604
605 if (NewState != DISABLE)
606 {
607 /* Set the BKSCD[i] bit */
608 DFSDM_Channelx -> CHAWSCDR |= DFSDM_SCDBreak_i;
609 }
610 else
611 {
612 /* Reset the BKSCD[i] bit */
613 DFSDM_Channelx -> CHAWSCDR &= ~(DFSDM_SCDBreak_i);
614 }
615 }
616
617 /**
618 * @brief Enables or disables the specified Break_i siganl to the specified DFSDM_Channelx.
619 * @param DFSDM_Channelx: specifies the channel to be selected.
620 * This parameter can be one of the following values :
621 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
622 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
623 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
624 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
625 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
626 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
627 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
628 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
629 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
630 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
631 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
632 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
633 * @param DFSDM_SCDBreak_i: where i can be a value from 0 to 3 to select the specified Break signal.
634 * @param NewState: new state of the selected DFSDM_SCDBreak_i.
635 * This parameter can be: ENABLE or DISABLE.
636 * @retval None
637 */
DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef * DFSDM_Channelx,uint32_t DFSDM_SCDBreak_i,FunctionalState NewState)638 void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState)
639 {
640 /* Check the parameters */
641 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
642 assert_param(IS_DFSDM_SCD_BREAK_SIGNAL(DFSDM_SCDBreak_i));
643 assert_param(IS_FUNCTIONAL_STATE(NewState));
644
645 if (NewState != DISABLE)
646 {
647 /* Set the BKSCD[i] bit */
648 DFSDM_Channelx -> CHAWSCDR |= DFSDM_SCDBreak_i;
649 }
650 else
651 {
652 /* Reset the BKSCD[i] bit */
653 DFSDM_Channelx -> CHAWSCDR &= ~(DFSDM_SCDBreak_i);
654 }
655 }
656
657 /**
658 * @brief Defines the threshold counter for the short circuit detector for the selected DFSDM_Channelx.
659 * @param DFSDM_Channelx: specifies the channel to be selected.
660 * This parameter can be one of the following values :
661 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
662 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
663 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
664 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
665 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
666 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
667 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
668 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
669 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
670 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
671 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
672 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
673 * @param DFSDM_SCDThreshold: The threshold counter, this parameter can be a value between 0 and 255.
674 * @retval None
675 */
DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef * DFSDM_Channelx,uint32_t DFSDM_SCDThreshold)676 void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold)
677 {
678 uint32_t tmpreg1 = 0;
679
680 /* Check the parameters */
681 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
682 assert_param(IS_DFSDM_CSD_THRESHOLD_VALUE(DFSDM_SCDThreshold));
683
684 /* Get the DFSDM_Channelx AWSCDR value */
685 tmpreg1 = DFSDM_Channelx -> CHAWSCDR;
686
687 /* Clear the SCDT bits */
688 tmpreg1 &= ~(DFSDM_CHAWSCDR_SCDT);
689
690 /* Set or Reset the SCDT bits */
691 tmpreg1 |= DFSDM_SCDThreshold;
692
693 /* Write to DFSDM Channelx AWSCDR */
694 DFSDM_Channelx -> CHAWSCDR = tmpreg1;
695 }
696
697 /**
698 * @brief Selects the channel to be guarded by the Analog watchdog for the selected DFSDMx,
699 * and select if the fast analog watchdog is enabled or not.
700 * @param DFSDMx: specifies the filter to be selected :
701 * This parameter can be one of the following values :
702 * @arg DFSDM1_0 : DFSDM 1 Filter 0
703 * @arg DFSDM1_1 : DFSDM 1 Filter 1
704 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
705 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
706 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
707 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
708 * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
709 * @param DFSDM_AWDFastMode: The analog watchdog fast mode.
710 * This parameter can be a value of @ref DFSDM_AWD_Fast_Mode_Selection.
711 * @retval None
712 */
DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_AWDChannelx,uint32_t DFSDM_AWDFastMode)713 void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode)
714 {
715 uint32_t tmpreg1 = 0;
716 uint32_t tmpreg2 = 0;
717
718 /* Check the parameters */
719 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
720 assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
721 assert_param(IS_DFSDM_AWD_MODE(DFSDM_AWDFastMode));
722
723 /* Get the DFSDMx CR2 value */
724 tmpreg1 = DFSDMx -> FLTCR2;
725
726 /* Clear the AWDCH bits */
727 tmpreg1 &= ~(DFSDM_FLTCR2_AWDCH);
728
729 /* Set or Reset the AWDCH bits */
730 tmpreg1 |= DFSDM_AWDChannelx;
731
732 /* Write to DFSDMx CR2 Register */
733 DFSDMx -> FLTCR2 |= tmpreg1;
734
735 /* Get the DFSDMx CR1 value */
736 tmpreg2 = DFSDMx->FLTCR1;
737
738 /* Clear the AWFSEL bit */
739 tmpreg2 &= ~(DFSDM_FLTCR1_AWFSEL);
740
741 /* Set or Reset the AWFSEL bit */
742 tmpreg2 |= DFSDM_AWDFastMode;
743
744 /* Write to DFSDMx CR1 Register */
745 DFSDMx->FLTCR1 = tmpreg2;
746 }
747
748 /**
749 * @brief Selects the channel to be guarded by the Analog watchdog of the selected DFSDMx, and the mode to be used.
750 * @param DFSDMx: specifies the filter to be selected :
751 * This parameter can be one of the following values :
752 * @arg DFSDM1_0 : DFSDM 1 Filter 0
753 * @arg DFSDM1_1 : DFSDM 1 Filter 1
754 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
755 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
756 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
757 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
758 * @param DFSDM_ExtremChannelx: where x can be a value from 0 to 7 to select the Channel to be connected
759 * to the Extremes detector.
760 * @retval None
761 */
DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_ExtremChannelx)762 void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx)
763 {
764 uint32_t tmpreg1 = 0;
765
766 /* Check the parameters */
767 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
768 assert_param(IS_DFSDM_EXTREM_CHANNEL(DFSDM_ExtremChannelx));
769
770 /* Get the DFSDMx CR2 value */
771 tmpreg1 = DFSDMx -> FLTCR2;
772
773 /* Clear the EXCH bits */
774 tmpreg1 &= ~(DFSDM_FLTCR2_EXCH);
775
776 /* Set or Reset the AWDCH bits */
777 tmpreg1 |= DFSDM_ExtremChannelx;
778
779 /* Write to DFSDMx CR2 Register */
780 DFSDMx -> FLTCR2 = tmpreg1;
781 }
782
783 /**
784 * @brief Returns the regular conversion data by the DFSDMx.
785 * @param DFSDMx: specifies the filter to be selected :
786 * This parameter can be one of the following values :
787 * @arg DFSDM1_0 : DFSDM 1 Filter 0
788 * @arg DFSDM1_1 : DFSDM 1 Filter 1
789 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
790 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
791 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
792 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
793 * @retval The converted regular data.
794 * @note This function returns a signed value.
795 */
DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef * DFSDMx)796 int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx)
797 {
798 uint32_t reg = 0;
799 int32_t value = 0;
800
801 /* Check the parameters */
802 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
803
804 /* Get value of data register for regular channel */
805 reg = DFSDMx -> FLTRDATAR;
806
807 /* Extract conversion value */
808 value = (((reg & 0xFFFFFF00) >> 8));
809
810 /* Return the conversion result */
811 return value;
812 }
813
814 /**
815 * @brief Returns the injected conversion data by the DFSDMx.
816 * @param DFSDMx: specifies the filter to be selected :
817 * This parameter can be one of the following values :
818 * @arg DFSDM1_0 : DFSDM 1 Filter 0
819 * @arg DFSDM1_1 : DFSDM 1 Filter 1
820 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
821 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
822 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
823 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
824 * @retval The converted regular data.
825 * @note This function returns a signed value.
826 */
DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef * DFSDMx)827 int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx)
828 {
829 uint32_t reg = 0;
830 int32_t value = 0;
831
832 /* Check the parameters */
833 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
834
835 /* Get value of data register for regular channel */
836 reg = DFSDMx -> FLTJDATAR;
837
838 /* Extract conversion value */
839 value = ((reg & 0xFFFFFF00) >> 8);
840
841 /* Return the conversion result */
842 return value;
843 }
844
845 /**
846 * @brief Returns the highest value converted by the DFSDMx.
847 * @param DFSDMx: specifies the filter to be selected :
848 * This parameter can be one of the following values :
849 * @arg DFSDM1_0 : DFSDM 1 Filter 0
850 * @arg DFSDM1_1 : DFSDM 1 Filter 1
851 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
852 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
853 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
854 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
855 * @retval The highest converted value.
856 * @note This function returns a signed value.
857 */
DFSDM_GetMaxValue(DFSDM_Filter_TypeDef * DFSDMx)858 int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx)
859 {
860 int32_t value = 0;
861
862 /* Check the parameters */
863 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
864
865 value = ((DFSDMx -> FLTEXMAX) >> 8);
866 /* Return the highest converted value */
867 return value;
868 }
869
870 /**
871 * @brief Returns the lowest value converted by the DFSDMx.
872 * @param DFSDMx: specifies the filter to be selected :
873 * This parameter can be one of the following values :
874 * @arg DFSDM1_0 : DFSDM 1 Filter 0
875 * @arg DFSDM1_1 : DFSDM 1 Filter 1
876 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
877 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
878 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
879 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
880 * @retval The lowest converted value.
881 * @note This function returns a signed value.
882 */
DFSDM_GetMinValue(DFSDM_Filter_TypeDef * DFSDMx)883 int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx)
884 {
885 int32_t value = 0;
886
887 /* Check the parameters */
888 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
889
890 value = ((DFSDMx -> FLTEXMIN) >> 8);
891 /* Return the lowest conversion value */
892 return value;
893 }
894
895 /**
896 * @brief Returns the number of channel on which is captured the highest converted data by the DFSDMx.
897 * @param DFSDMx: specifies the filter to be selected :
898 * This parameter can be one of the following values :
899 * @arg DFSDM1_0 : DFSDM 1 Filter 0
900 * @arg DFSDM1_1 : DFSDM 1 Filter 1
901 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
902 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
903 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
904 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
905 * @retval The highest converted value.
906 */
DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef * DFSDMx)907 int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx)
908 {
909 /* Check the parameters */
910 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
911
912 /* Return the highest converted value */
913 return ((DFSDMx -> FLTEXMAX) & (~DFSDM_FLTEXMAX_EXMAXCH));
914 }
915
916 /**
917 * @brief Returns the number of channel on which is captured the lowest converted data by the DFSDMx.
918 * @param DFSDMx: specifies the filter to be selected :
919 * This parameter can be one of the following values :
920 * @arg DFSDM1_0 : DFSDM 1 Filter 0
921 * @arg DFSDM1_1 : DFSDM 1 Filter 1
922 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
923 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
924 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
925 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
926 * @retval The lowest converted value.
927 */
DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef * DFSDMx)928 int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx)
929 {
930 /* Check the parameters */
931 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
932
933 /* Return the lowest converted value */
934 return ((DFSDMx -> FLTEXMIN) & (~DFSDM_FLTEXMIN_EXMINCH));
935 }
936
937 /**
938 * @brief Returns the conversion time (in 28-bit timer unit) for DFSDMx.
939 * @param DFSDMx: specifies the filter to be selected :
940 * This parameter can be one of the following values :
941 * @arg DFSDM1_0 : DFSDM 1 Filter 0
942 * @arg DFSDM1_1 : DFSDM 1 Filter 1
943 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
944 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
945 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
946 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
947 * @retval Conversion time.
948 */
DFSDM_GetConversionTime(DFSDM_Filter_TypeDef * DFSDMx)949 uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx)
950 {
951 /* Check the parameters */
952 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
953
954 /* Return the lowest converted value */
955 return ((DFSDMx -> FLTCNVTIMR >> 4) & 0x0FFFFFFF);
956 }
957
958 /**
959 * @brief Configures Sinc Filter for the Analog watchdog by setting
960 * the Sinc filter order and the Oversampling ratio for the specified DFSDM_Channelx.
961 * @param DFSDM_Channelx: specifies the channel to be selected.
962 * This parameter can be one of the following values :
963 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
964 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
965 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
966 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
967 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
968 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
969 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
970 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
971 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
972 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
973 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
974 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
975 * @param DFSDM_AWDSincOrder: The Sinc Filter order this parameter can be a value of @ref DFSDM_AWD_Sinc_Order.
976 * @param DFSDM_AWDSincOverSampleRatio: The Filter Oversampling ratio, this parameter can be a value between 1 and 32.
977 * @retval None
978 */
DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef * DFSDM_Channelx,uint32_t DFSDM_AWDSincOrder,uint32_t DFSDM_AWDSincOverSampleRatio)979 void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio)
980 {
981 uint32_t tmpreg1 = 0;
982
983 /* Check the parameters */
984 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
985 assert_param(IS_DFSDM_AWD_SINC_ORDER(DFSDM_AWDSincOrder));
986 assert_param(IS_DFSDM_AWD_OVRSMPL_RATIO(DFSDM_AWDSincOverSampleRatio));
987
988 /* Get the DFSDM_Channelx CHAWSCDR value */
989 tmpreg1 = DFSDM_Channelx -> CHAWSCDR;
990
991 /* Clear the FORD and FOSR bits */
992 tmpreg1 &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
993
994 /* Set or Reset the SCDT bits */
995 tmpreg1 |= (DFSDM_AWDSincOrder | ((DFSDM_AWDSincOverSampleRatio -1) << 16)) ;
996
997 /* Write to DFSDM Channelx CHAWSCDR */
998 DFSDM_Channelx -> CHAWSCDR = tmpreg1;
999 }
1000
1001 /**
1002 * @brief Returns the last Analog Watchdog Filter conversion result data for channelx.
1003 * @param DFSDM_Channelx: specifies the channel to be selected.
1004 * This parameter can be one of the following values :
1005 * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
1006 * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
1007 * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
1008 * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
1009 * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
1010 * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
1011 * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
1012 * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
1013 * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
1014 * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
1015 * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
1016 * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
1017 * @retval The Data conversion value.
1018 */
DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef * DFSDM_Channelx)1019 uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx)
1020 {
1021 /* Check the parameters */
1022 assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
1023
1024 /* Return the last analog watchdog filter conversion value */
1025 return DFSDM_Channelx -> CHWDATAR;
1026 }
1027
1028
1029 /**
1030 * @brief Configures the High Threshold and the Low threshold for the Analog watchdog of the selected DFSDMx.
1031 * @param DFSDMx: specifies the filter to be selected :
1032 * This parameter can be one of the following values :
1033 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1034 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1035 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1036 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1037 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1038 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1039 * @param DFSDM_HighThreshold: High threshold value. This parameter can be value between 0 and 0xFFFFFF.
1040 * @param DFSDM_LowThreshold: Low threshold value. This parameter can be value between 0 and 0xFFFFFF.
1041 * @retval None.
1042 * @note In case of channels transceivers monitoring (Analog Watchdog fast mode Enabled)),
1043 * only the higher 16 bits define the 16-bit threshold compared with analog watchdog filter output.
1044 */
1045
DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_HighThreshold,uint32_t DFSDM_LowThreshold)1046 void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold)
1047 {
1048 uint32_t tmpreg1 = 0;
1049 uint32_t tmpreg2 = 0;
1050
1051 /* Check the parameters */
1052 assert_param(IS_DFSDM_HIGH_THRESHOLD(DFSDM_HighThreshold));
1053 assert_param(IS_DFSDM_LOW_THRESHOLD(DFSDM_LowThreshold));
1054
1055 /* Get the DFSDMx AWHTR value */
1056 tmpreg1 = DFSDMx -> FLTAWHTR;
1057
1058 /* Clear the AWHT bits */
1059 tmpreg1 &= ~(DFSDM_FLTAWHTR_AWHT);
1060
1061 /* Set or Reset the AWHT bits */
1062 tmpreg1 |= (DFSDM_HighThreshold << 8 );
1063
1064 /* Write to DFSDMx AWHTR Register */
1065 DFSDMx -> FLTAWHTR = tmpreg1;
1066
1067 /* Get the DFSDMx AWLTR value */
1068 tmpreg2 = DFSDMx -> FLTAWLTR;
1069
1070 /* Clear the AWLTR bits */
1071 tmpreg2 &= ~(DFSDM_FLTAWLTR_AWLT);
1072
1073 /* Set or Reset the AWLTR bits */
1074 tmpreg2 |= (DFSDM_LowThreshold << 8 );
1075
1076 /* Write to DFSDMx AWLTR Register */
1077 DFSDMx -> FLTAWLTR = tmpreg2;
1078 }
1079
1080 /**
1081 * @brief Selects the injected channel for the selected DFSDMx.
1082 * @param DFSDMx: specifies the filter to be selected :
1083 * This parameter can be one of the following values :
1084 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1085 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1086 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1087 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1088 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1089 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1090 * @param DFSDM_InjectedChannelx: where x can be a value from 0 to 7 to select the Channel to be configuraed as
1091 * injected channel.
1092 * @retval None
1093 * @note User can select up to 8 channels.
1094 */
DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_InjectedChannelx)1095 void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx)
1096 {
1097 uint32_t tmpreg1 = 0;
1098
1099 /* Check the parameters */
1100 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1101 assert_param(IS_DFSDM_INJECT_CHANNEL(DFSDM_InjectedChannelx));
1102
1103 /* Get the DFSDMx JCHGR value */
1104 tmpreg1 = DFSDMx -> FLTJCHGR;
1105
1106 /* Clear the JCHGR bits */
1107 tmpreg1 &= ~(DFSDM_FLTJCHGR_JCHG);
1108
1109 /* Set or Reset the JCHGR bits */
1110 tmpreg1 |= DFSDM_InjectedChannelx;
1111
1112 /* Write to DFSDMx JCHGR Register */
1113 DFSDMx -> FLTJCHGR |= tmpreg1;
1114 }
1115
1116 /**
1117 * @brief Selects the regular channel for the selected DFSDMx.
1118 * @param DFSDMx: specifies the filter to be selected :
1119 * This parameter can be one of the following values :
1120 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1121 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1122 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1123 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1124 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1125 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1126 * @param DFSDM_RegularChannelx: where x can be a value from 0 to 7 to select the Channel to be configurated as
1127 * regular channel.
1128 * @retval None
1129 * @note User can select only one channel.
1130 */
DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_RegularChannelx)1131 void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx)
1132 {
1133 uint32_t tmpreg1 = 0;
1134
1135 /* Check the parameters */
1136 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1137 assert_param(IS_DFSDM_REGULAR_CHANNEL(DFSDM_RegularChannelx));
1138
1139 /* Get the DFSDMx CR1 value */
1140 tmpreg1 = DFSDMx -> FLTCR1;
1141
1142 /* Clear the RCH bits */
1143 tmpreg1 &= ~(DFSDM_FLTCR1_RCH);
1144
1145 /* Set or Reset the RCH bits */
1146 tmpreg1 |= DFSDM_RegularChannelx;
1147
1148 /* Write to DFSDMx CR1 Register */
1149 DFSDMx -> FLTCR1 = tmpreg1;
1150 }
1151
1152 /**
1153 * @brief Starts a software start for the injected group of channels of the selected DFSDMx.
1154 * @param DFSDMx: specifies the filter to be selected :
1155 * This parameter can be one of the following values :
1156 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1157 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1158 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1159 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1160 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1161 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1162 * @retval None
1163 */
DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef * DFSDMx)1164 void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx)
1165 {
1166 /* Check the parameters */
1167 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1168
1169 /* Write 1 to DFSDMx CR1 RSWSTAR bit */
1170 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
1171 }
1172
1173 /**
1174 * @brief Starts a software start of the regular channel of the selected DFSDMx.
1175 * @param DFSDMx: specifies the filter to be selected :
1176 * This parameter can be one of the following values :
1177 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1178 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1179 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1180 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1181 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1182 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1183 * @retval None
1184 */
DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef * DFSDMx)1185 void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx)
1186 {
1187 /* Check the parameters */
1188 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1189
1190 /* Write 1 to DFSDMx CR1 RSWSTAR bit */
1191 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
1192 }
1193
1194 /**
1195 * @brief Selects the Trigger signal to launch the injected conversions of the selected DFSDMx.
1196 * @param DFSDMx: specifies the filter to be selected :
1197 * This parameter can be one of the following values :
1198 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1199 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1200 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1201 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1202 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1203 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1204 * @param DFSDM_InjectedTrigger: the trigger signal.
1205 * This parameter can be a value of: @ref DFSDM_Injected_Trigger_signal
1206 * @param DFSDM_TriggerEdge: the edge of the selected trigger
1207 * This parameter can be a value of: @ref DFSDM_Trigger_Edge_selection
1208 * @retval None.
1209 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1210 * to disable the filter.
1211 */
DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_Trigger,uint32_t DFSDM_TriggerEdge)1212 void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge)
1213 {
1214 uint32_t tmpreg1 = 0;
1215
1216 /* Check the parameters */
1217 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1218
1219 if (DFSDMx == DFSDM0)
1220 {
1221 assert_param(IS_DFSDM0_INJ_TRIGGER(DFSDM_Trigger));
1222 }
1223 else
1224 {
1225 assert_param(IS_DFSDM1_INJ_TRIGGER(DFSDM_Trigger));
1226 }
1227
1228 assert_param(IS_DFSDM_TRIGGER_EDGE(DFSDM_TriggerEdge));
1229
1230 /* Get the DFSDMx CR1 value */
1231 tmpreg1 = DFSDMx -> FLTCR1;
1232
1233 /* Clear the JEXTSEL & JEXTEN bits */
1234 tmpreg1 &= ~(DFSDM_FLTCR1_JEXTSEL | DFSDM_FLTCR1_JEXTEN);
1235
1236 /* Set or Reset the JEXTSEL & JEXTEN bits */
1237 tmpreg1 |= (DFSDM_Trigger | DFSDM_TriggerEdge);
1238
1239 /* Write to DFSDMx CR1 Register */
1240 DFSDMx -> FLTCR1 = tmpreg1;
1241 }
1242
1243 /**
1244 * @brief Starts an injected conversion synchronously when in DFSDM0
1245 * an injected conversion started by software.
1246 * @param DFSDMx: specifies the filter to be selected :
1247 * This parameter can be one of the following values :
1248 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1249 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1250 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1251 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1252 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1253 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1254 * @retval None
1255 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1256 * to disable the filter.
1257 */
DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef * DFSDMx)1258 void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx)
1259 {
1260 /* Check the parameters */
1261 assert_param(IS_DFSDM_SYNC_FILTER(DFSDMx));
1262
1263 /* Write 1 to DFSDMx CR1 JSYNC bit */
1264 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_JSYNC;
1265 }
1266
1267 /**
1268 * @brief Starts a regular conversion synchronously when in DFSDM0
1269 * a regular conversion started by software.
1270 * @param DFSDMx: specifies the filter to be selected :
1271 * This parameter can be one of the following values :
1272 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1273 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1274 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1275 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1276 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1277 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1278 * @retval None
1279 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1280 * to disable the filter.
1281 */
DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef * DFSDMx)1282 void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx)
1283 {
1284 /* Check the parameters */
1285 assert_param(IS_DFSDM_SYNC_FILTER(DFSDMx));
1286
1287 /* Write 1 to DFSDMx CR1 RSYNC bit */
1288 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RSYNC;
1289 }
1290
1291 /**
1292 * @brief Enables or Disables the continue mode for Regular conversion for the selected filter DFSDMx.
1293 * @param DFSDMx: specifies the filter to be selected :
1294 * This parameter can be one of the following values :
1295 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1296 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1297 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1298 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1299 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1300 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1301 * @param NewState: new state of the Continuous mode.
1302 * This parameter can be: ENABLE or DISABLE.
1303 * @retval None
1304 */
DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef * DFSDMx,FunctionalState NewState)1305 void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
1306 {
1307 /* Check the parameters */
1308 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1309 assert_param(IS_FUNCTIONAL_STATE(NewState));
1310
1311 if (NewState != DISABLE)
1312 {
1313 /* Enable the RCONT bit */
1314 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RCONT;
1315 }
1316 else
1317 {
1318 /* Disable the RCONT bit */
1319 DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_RCONT);
1320 }
1321 }
1322
1323 /**
1324 * @brief Enables or Disables the Fast mode for the selected filter DFSDMx.
1325 * @param DFSDMx: specifies the filter to be selected :
1326 * This parameter can be one of the following values :
1327 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1328 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1329 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1330 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1331 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1332 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1333 * @param NewState: new state of the Fast mode.
1334 * This parameter can be: ENABLE or DISABLE.
1335 * @retval None
1336 * @note If just a single channel is selected in continuous mode (either by executing a regular
1337 * conversion or by executing a injected conversion with only one channel selected),
1338 * the sampling rate can be increased several times by enabling the fast mode.
1339 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1340 * to disable the filter.
1341 */
DFSDM_FastModeCmd(DFSDM_Filter_TypeDef * DFSDMx,FunctionalState NewState)1342 void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
1343 {
1344 /* Check the parameters */
1345 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1346 assert_param(IS_FUNCTIONAL_STATE(NewState));
1347
1348 if (NewState != DISABLE)
1349 {
1350 /* Enable the FAST bit */
1351 DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_FAST;
1352 }
1353 else
1354 {
1355 /* Disable the FAST bit */
1356 DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
1357 }
1358 }
1359
1360 /**
1361 * @brief Selects the injected conversions mode for the selected DFSDMx.
1362 * Injected conversions can operates in Single mode or Scan mode.
1363 * @param DFSDMx: specifies the filter to be selected :
1364 * This parameter can be one of the following values :
1365 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1366 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1367 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1368 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1369 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1370 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1371 * @param DFSDM_InjectConvMode: The injected conversion mode, this parameter can be:
1372 * @arg DFSDM_InjectConvMode_Single
1373 * @arg DFSDM_InjectConvMode_Scan
1374 * @retval None.
1375 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1376 * to disable the filter.
1377 */
DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_InjectConvMode)1378 void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode)
1379 {
1380 /* Check the parameters */
1381 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1382 assert_param(IS_DFSDM_INJ_CONV_MODE(DFSDM_InjectConvMode));
1383
1384 /* Clear the JSCAN bit */
1385 DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
1386
1387 /* Write to DFSDMx CR1 Register */
1388 DFSDMx -> FLTCR1 |= DFSDM_InjectConvMode;
1389 }
1390
1391 /**
1392 * @brief Enables or Disables the DMA to read data for the injected channel group of the selected filter DFSDMx.
1393 * @param DFSDMx: specifies the filter to be selected :
1394 * This parameter can be one of the following values :
1395 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1396 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1397 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1398 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1399 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1400 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1401 * @param DFSDM_DMAConversionMode: Selects the mode to be configured for DMA read .
1402 * @arg DFSDM_DMAConversionMode_Regular: DMA channel Enabled/Disabled to read data for the regular conversion
1403 * @arg DFSDM_DMAConversionMode_Injected: DMA channel Enabled/Disabled to read data for the Injected conversion
1404 * @param NewState: new state of the DMA channel.
1405 * This parameter can be: ENABLE or DISABLE.
1406 * @retval None.
1407 * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
1408 * to disable the filter.
1409 */
DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_DMAConversionMode,FunctionalState NewState)1410 void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState)
1411 {
1412 /* Check the parameters */
1413 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1414 assert_param(IS_DFSDM_CONVERSION_MODE(DFSDM_DMAConversionMode));
1415 assert_param(IS_FUNCTIONAL_STATE(NewState));
1416
1417 if (NewState != DISABLE)
1418 {
1419 /* Enable the JDMAEN or RDMAEN bit */
1420 DFSDMx -> FLTCR1 |= (DFSDM_FLTCR1_JDMAEN << DFSDM_DMAConversionMode) ;
1421 }
1422 else
1423 {
1424 /* Disable the JDMAEN or RDMAEN bit */
1425 DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN << DFSDM_DMAConversionMode);
1426 }
1427 }
1428
1429 /** @defgroup DFSDM_Group3 Interrupts and flags management functions
1430 * @brief Interrupts and flags management functions
1431 *
1432 @verbatim
1433 ===============================================================================
1434 Interrupts and flags management functions
1435 ===============================================================================
1436 This section provides functions allowing to configure the DFSDM Interrupts, get
1437 the status and clear flags bits.
1438
1439 The LPT provides 7 Flags and Interrupts sources (2 flags and Interrupt sources
1440 are available only on LPT peripherals equipped with encoder mode interface)
1441
1442 Flags and Interrupts sources:
1443 =============================
1444 1. End of injected conversion.
1445 2. End of regular conversion.
1446 3. Injected data overrun.
1447 4. Regular data overrun.
1448 5. Analog watchdog.
1449 6. Short circuit detector.
1450 7. Channel clock absence
1451
1452 - To enable a specific interrupt source, use "DFSDM_ITConfig",
1453 "DFSDM_ITClockAbsenceCmd" and "DFSDM_ITShortCircuitDetectorCmd" functions.
1454 - To check if an interrupt was occurred, call "DFSDM_GetITStatus","DFSDM_GetClockAbsenceITStatusfunction"
1455 and "DFSDM_GetGetShortCircuitITStatus" functions and read returned values.
1456 - To get a flag status, call the "DFSDM_GetFlagStatus" ,"DFSDM_GetClockAbsenceFlagStatus" ,"DFSDM_GetShortCircuitFlagStatus"
1457 and "DFSDM_GetWatchdogFlagStatus" functions and read the returned value.
1458 - To clear a flag or an interrupt, use DFSDM_ClearFlag,DFSDM_ClearClockAbsenceFlag,
1459 DFSDM_ClearShortCircuitFlag,DFSDM_ClearAnalogWatchdogFlag functions with the
1460 corresponding flag (interrupt).
1461
1462 @endverbatim
1463 * @{
1464 */
1465
1466 /**
1467 * @brief Enables or disables the specified DFSDMx interrupts.
1468 * @param DFSDMx: specifies the filter to be selected :
1469 * This parameter can be one of the following values :
1470 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1471 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1472 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1473 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1474 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1475 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1476 * @param DFSDM_IT: specifies the DFSDM interrupts sources to be enabled or disabled.
1477 * This parameter can be any combination of the following values:
1478 * @arg DFSDM_IT_JEOC: End of injected conversion Interrupt source
1479 * @arg DFSDM_IT_REOC: End of regular conversion Interrupt source
1480 * @arg DFSDM_IT_JOVR: Injected data overrun Interrupt source
1481 * @arg DFSDM_IT_ROVR: Regular data overrun Interrupt source
1482 * @arg DFSDM_IT_AWD : Analog watchdog Interrupt source
1483 * @param NewState: new state of the DFSDM interrupts.
1484 * This parameter can be: ENABLE or DISABLE.
1485 * @retval None
1486 */
DFSDM_ITConfig(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_IT,FunctionalState NewState)1487 void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState)
1488 {
1489 /* Check the parameters */
1490 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1491 assert_param(IS_DFSDM_IT(DFSDM_IT));
1492 assert_param(IS_FUNCTIONAL_STATE(NewState));
1493
1494 if (NewState != DISABLE)
1495 {
1496 /* Enable the Interrupt sources */
1497 DFSDMx->FLTCR2 |= DFSDM_IT;
1498 }
1499 else
1500 {
1501 /* Disable the Interrupt sources */
1502 DFSDMx->FLTCR2 &= ~(DFSDM_IT);
1503 }
1504 }
1505
1506 #if defined(STM32F412xG)
1507 /**
1508 * @brief Enables or disables the Clock Absence Interrupt.
1509 * @param NewState: new state of the interrupt.
1510 * This parameter can be: ENABLE or DISABLE.
1511 * @retval None
1512 */
DFSDM_ITClockAbsenceCmd(FunctionalState NewState)1513 void DFSDM_ITClockAbsenceCmd(FunctionalState NewState)
1514 {
1515 /* Check the parameters */
1516 assert_param(IS_FUNCTIONAL_STATE(NewState));
1517
1518 if (NewState != DISABLE)
1519 {
1520 /* Enable the Interrupt source */
1521 DFSDM1_0->FLTCR2 |= DFSDM_IT_CKAB;
1522 }
1523 else
1524 {
1525 /* Disable the Interrupt source */
1526 DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
1527 }
1528 }
1529
1530 /**
1531 * @brief Enables or disables the Short Circuit Detector Interrupt.
1532 * @param NewState: new state of the interrupt.
1533 * This parameter can be: ENABLE or DISABLE.
1534 * @retval None
1535 */
DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState)1536 void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState)
1537 {
1538 /* Check the parameters */
1539 assert_param(IS_FUNCTIONAL_STATE(NewState));
1540
1541 if (NewState != DISABLE)
1542 {
1543 /* Enable the Interrupt source */
1544 DFSDM1_0->FLTCR2 |= DFSDM_IT_SCD;
1545 }
1546 else
1547 {
1548 /* Disable the Interrupt source */
1549 DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_SCD);
1550 }
1551 }
1552 #endif /* STM32F412xG */
1553
1554 #if defined(STM32F413_423xx)
1555 /**
1556 * @brief Enables or disables the Clock Absence Interrupt.
1557 * @param Instance: select the instance of DFSDM
1558 * This parameter can be: 1 or 2.
1559 * @param NewState: new state of the interrupt.
1560 * This parameter can be: ENABLE or DISABLE.
1561 * @retval None
1562 */
DFSDM_ITClockAbsenceCmd(uint32_t Instance,FunctionalState NewState)1563 void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState)
1564 {
1565 /* Check the parameters */
1566 assert_param(IS_FUNCTIONAL_STATE(NewState));
1567 if(Instance == 1)
1568 {
1569 if (NewState != DISABLE)
1570 {
1571 /* Enable the Interrupt source */
1572 DFSDM1_0->FLTCR2 |= DFSDM_IT_CKAB;
1573 }
1574 else
1575 {
1576 /* Disable the Interrupt source */
1577 DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
1578 }
1579 }
1580 else /* DFSDM2 */
1581 {
1582 if (NewState != DISABLE)
1583 {
1584 /* Enable the Interrupt source */
1585 DFSDM2_0->FLTCR2 |= DFSDM_IT_CKAB;
1586 }
1587 else
1588 {
1589 /* Disable the Interrupt source */
1590 DFSDM2_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
1591 }
1592 }
1593 }
1594
1595 /**
1596 * @brief Enables or disables the Short Circuit Detector Interrupt.
1597 * @param Instance: select the instance of DFSDM
1598 * This parameter can be: 1 or 2.
1599 * @param NewState: new state of the interrupt.
1600 * This parameter can be: ENABLE or DISABLE.
1601 * @retval None
1602 */
DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance,FunctionalState NewState)1603 void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState)
1604 {
1605 /* Check the parameters */
1606 assert_param(IS_FUNCTIONAL_STATE(NewState));
1607
1608 if(Instance == 1)
1609 {
1610 if (NewState != DISABLE)
1611 {
1612 /* Enable the Interrupt source */
1613 DFSDM1_0->FLTCR2 |= DFSDM_IT_SCD;
1614 }
1615 else
1616 {
1617 /* Disable the Interrupt source */
1618 DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_SCD);
1619 }
1620 }
1621 else /* DFSDM2 */
1622 {
1623 if (NewState != DISABLE)
1624 {
1625 /* Enable the Interrupt source */
1626 DFSDM2_0->FLTCR2 |= DFSDM_IT_SCD;
1627 }
1628 else
1629 {
1630 /* Disable the Interrupt source */
1631 DFSDM2_0->FLTCR2 &= ~(DFSDM_IT_SCD);
1632 }
1633 }
1634
1635 }
1636 #endif /* STM32F413_423xx */
1637
1638 /**
1639 * @brief Checks whether the specified DFSDM flag is set or not.
1640 * @param DFSDMx: specifies the filter to be selected :
1641 * This parameter can be one of the following values :
1642 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1643 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1644 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1645 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1646 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1647 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1648 * @param LPT_FLAG: specifies the flag to check.
1649 * This parameter can be any combination of the following values:
1650 * @arg DFSDM_FLAG_JEOC: End of injected conversion Flag
1651 * @arg DFSDM_FLAG_REOC: End of regular conversion Flag
1652 * @arg DFSDM_FLAG_JOVR: Injected data overrun Flag
1653 * @arg DFSDM_FLAG_ROVR: Regular data overrun Flag
1654 * @arg DFSDM_FLAG_AWD: Analog watchdog Flag
1655 * @arg DFSDM_FLAG_JCIP: Injected conversion in progress status
1656 * @arg DFSDM_FLAG_RCIP: Regular conversion in progress status
1657 * @retval None
1658 */
DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_FLAG)1659 FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG)
1660 {
1661 ITStatus bitstatus = RESET;
1662
1663 /* Check the parameters */
1664 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1665 assert_param(IS_DFSDM_FLAG(DFSDM_FLAG));
1666
1667 if ((DFSDMx->FLTISR & DFSDM_FLAG) != RESET )
1668 {
1669 bitstatus = SET;
1670 }
1671 else
1672 {
1673 bitstatus = RESET;
1674 }
1675 return bitstatus;
1676 }
1677
1678 #if defined(STM32F412xG)
1679 /**
1680 * @brief Checks whether the specified Clock Absence Channel flag is set or not.
1681 * @param DFSDM_FLAG_CLKAbsence: specifies the flag to check.
1682 * This parameter can be a value of @ref DFSDM_Clock_Absence_Flag_Definition
1683 * @retval None
1684 */
DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence)1685 FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence)
1686 {
1687 ITStatus bitstatus = RESET;
1688
1689 /* Check the parameters */
1690 assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
1691
1692 if((DFSDM1_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
1693 {
1694 bitstatus = SET;
1695 }
1696 else
1697 {
1698 bitstatus = RESET;
1699 }
1700 return bitstatus;
1701 }
1702
1703 /**
1704 * @brief Checks whether the specified Short Circuit Channel Detector flag is set or not.
1705 * @param DFSDM_FLAG_SCD: specifies the flag to check.
1706 * This parameter can be a value of @ref DFSDM_SCD_Flag_Definition
1707 * @retval None
1708 */
DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD)1709 FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD)
1710 {
1711 ITStatus bitstatus = RESET;
1712
1713 /* Check the parameters */
1714 assert_param(IS_DFSDM_SCD_FLAG(DFSDM_FLAG_SCD));
1715
1716 if ((DFSDM1_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
1717 {
1718 bitstatus = SET;
1719 }
1720 else
1721 {
1722 bitstatus = RESET;
1723 }
1724
1725 return bitstatus;
1726 }
1727 #endif /* STM32F412xG */
1728 #if defined(STM32F413_423xx)
1729 /**
1730 * @brief Checks whether the specified Clock Absence Channel flag is set or not.
1731 * @param Instance: select the instance of DFSDM
1732 * This parameter can be: 1 or 2.
1733 * @param DFSDM_FLAG_CLKAbsence: specifies the flag to check.
1734 * This parameter can be a value of @ref DFSDM_Clock_Absence_Flag_Definition
1735 * @retval None
1736 */
DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance,uint32_t DFSDM_FLAG_CLKAbsence)1737 FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence)
1738 {
1739 ITStatus bitstatus = RESET;
1740
1741 /* Check the parameters */
1742 assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
1743
1744 if(Instance == 1)
1745 {
1746 if((DFSDM1_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
1747 {
1748 bitstatus = SET;
1749 }
1750 else
1751 {
1752 bitstatus = RESET;
1753 }
1754 }
1755 else /* DFSDM2 */
1756 {
1757 /* Check the parameters */
1758 assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
1759
1760 if((DFSDM2_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
1761 {
1762 bitstatus = SET;
1763 }
1764 else
1765 {
1766 bitstatus = RESET;
1767 }
1768 }
1769 return bitstatus;
1770 }
1771
1772 /**
1773 * @brief Checks whether the specified Short Circuit Channel Detector flag is set or not.
1774 * @param Instance: select the instance of DFSDM
1775 * This parameter can be: 1 or 2.
1776 * @param DFSDM_FLAG_SCD: specifies the flag to check.
1777 * This parameter can be a value of @ref DFSDM_SCD_Flag_Definition
1778 * @retval None
1779 */
DFSDM_GetShortCircuitFlagStatus(uint32_t Instance,uint32_t DFSDM_FLAG_SCD)1780 FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD)
1781 {
1782 ITStatus bitstatus = RESET;
1783
1784 /* Check the parameters */
1785 assert_param(IS_DFSDM_SCD_FLAG(DFSDM_FLAG_SCD));
1786
1787 if(Instance == 1)
1788 {
1789 if ((DFSDM1_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
1790 {
1791 bitstatus = SET;
1792 }
1793 else
1794 {
1795 bitstatus = RESET;
1796 }
1797 }
1798 else /* DFSDM2 */
1799 {
1800 if ((DFSDM2_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
1801 {
1802 bitstatus = SET;
1803 }
1804 else
1805 {
1806 bitstatus = RESET;
1807 }
1808 }
1809 return bitstatus;
1810 }
1811 #endif /* STM32F413_423xx */
1812 /**
1813 * @brief Checks whether the specified Watchdog threshold flag is set or not.
1814 * @param DFSDMx: specifies the filter to be selected :
1815 * This parameter can be one of the following values :
1816 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1817 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1818 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1819 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1820 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1821 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1822 * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
1823 * @param DFSDM_Threshold: specifies the Threshold.
1824 * This parameter can be a value of @ref DFSDM_Threshold_Selection.
1825 * @retval None
1826 */
DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_AWDChannelx,uint8_t DFSDM_Threshold)1827 FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold)
1828 {
1829 ITStatus bitstatus = RESET;
1830
1831 /* Check the parameters */
1832 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1833 assert_param(IS_DFSDM_Threshold(DFSDM_Threshold));
1834 assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
1835
1836 if ((DFSDMx->FLTAWSR & ((DFSDM_AWDChannelx >> 16) << DFSDM_Threshold) ) != RESET)
1837 {
1838 bitstatus = SET;
1839 }
1840 else
1841 {
1842 bitstatus = RESET;
1843 }
1844 return bitstatus;
1845 }
1846
1847 /**
1848 * @brief Clears the DFSDMx's pending flag.
1849 * @param DFSDMx: specifies the filter to be selected :
1850 * This parameter can be one of the following values :
1851 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1852 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1853 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1854 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1855 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1856 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1857 * @param DFSDM_CLEARF: specifies the pending bit to clear.
1858 * This parameter can be any combination of the following values:
1859 * @arg DFSDM_CLEARF_JOVR: Injected data overrun Clear Flag
1860 * @arg DFSDM_CLEARF_ROVR: Regular data overrun Clear Flag
1861 * @retval None
1862 */
DFSDM_ClearFlag(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_CLEARF)1863 void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF)
1864 {
1865 /* Check the parameters */
1866 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1867 assert_param(IS_DFSDM_CLEAR_FLAG(DFSDM_CLEARF));
1868
1869 /* Clear the pending Flag Bit */
1870 DFSDMx->FLTICR |= DFSDM_CLEARF;
1871 }
1872
1873 #if defined(STM32F412xG)
1874 /**
1875 * @brief Clears the DFSDMx's pending Clock Absence Channel flag.
1876 * @param DFSDM_CLEARF_CLKAbsence: specifies the pending bit to clear.
1877 * This parameter can be any combination of @ref DFSDM_Clear_ClockAbs_Flag_Definition
1878 * @retval None
1879 */
DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence)1880 void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence)
1881 {
1882 /* Check the parameters */
1883 assert_param(IS_DFSDM_CLK_ABS_CLEARF(DFSDM_CLEARF_CLKAbsence));
1884
1885 /* Clear the IT pending Flag Bit */
1886 DFSDM1_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
1887 }
1888
1889 /**
1890 * @brief Clears the DFSDMx's pending Short circuit Channel flag.
1891 * @param DFSDM_CLEARF_SCD: specifies the pending bit to clear.
1892 * This parameter can be any combination of @ref DFSDM_Clear_Short_Circuit_Flag_Definition
1893 * @retval None
1894 */
DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD)1895 void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD)
1896 {
1897 /* Check the parameters */
1898 assert_param(IS_DFSDM_SCD_CHANNEL_FLAG(DFSDM_CLEARF_SCD));
1899
1900 /* Clear the pending Flag Bit */
1901 DFSDM1_0->FLTICR |= DFSDM_CLEARF_SCD;
1902 }
1903 #endif /* STM32F412xG */
1904
1905 #if defined(STM32F413_423xx)
1906 /**
1907 * @brief Clears the DFSDMx's pending Clock Absence Channel flag.
1908 * @param Instance: select the instance of DFSDM
1909 * This parameter can be: 1 or 2.
1910 * @param DFSDM_CLEARF_CLKAbsence: specifies the pending bit to clear.
1911 * This parameter can be any combination of @ref DFSDM_Clear_ClockAbs_Flag_Definition
1912 * @retval None
1913 */
DFSDM_ClearClockAbsenceFlag(uint32_t Instance,uint32_t DFSDM_CLEARF_CLKAbsence)1914 void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence)
1915 {
1916 /* Check the parameters */
1917 assert_param(IS_DFSDM_CLK_ABS_CLEARF(DFSDM_CLEARF_CLKAbsence));
1918
1919 if(Instance == 1)
1920 {
1921 /* Clear the IT pending Flag Bit */
1922 DFSDM1_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
1923 }
1924 else /* DFSDM2 */
1925 {
1926 /* Clear the IT pending Flag Bit */
1927 DFSDM2_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
1928 }
1929 }
1930
1931 /**
1932 * @brief Clears the DFSDMx's pending Short circuit Channel flag.
1933 * @param Instance: select the instance of DFSDM
1934 * This parameter can be: 1 or 2.
1935 * @param DFSDM_CLEARF_SCD: specifies the pending bit to clear.
1936 * This parameter can be any combination of @ref DFSDM_Clear_Short_Circuit_Flag_Definition
1937 * @retval None
1938 */
DFSDM_ClearShortCircuitFlag(uint32_t Instance,uint32_t DFSDM_CLEARF_SCD)1939 void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD)
1940 {
1941 /* Check the parameters */
1942 assert_param(IS_DFSDM_SCD_CHANNEL_FLAG(DFSDM_CLEARF_SCD));
1943
1944 if(Instance == 1)
1945 {
1946 /* Clear the pending Flag Bit */
1947 DFSDM1_0->FLTICR |= DFSDM_CLEARF_SCD;
1948 }
1949 else
1950 {
1951 /* Clear the pending Flag Bit */
1952 DFSDM2_0->FLTICR |= DFSDM_CLEARF_SCD;
1953 }
1954 }
1955 #endif /* STM32F413_423xx */
1956 /**
1957 * @brief Clears the DFSDMx's pending Analog watchdog Channel flag.
1958 * @param DFSDMx: specifies the filter to be selected :
1959 * This parameter can be one of the following values :
1960 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1961 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1962 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1963 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1964 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1965 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1966 * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
1967 * @param DFSDM_Threshold: specifies the Threshold.
1968 * This parameter can be a value of @ref DFSDM_Threshold_Selection.
1969 * @retval None
1970 */
DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_AWDChannelx,uint8_t DFSDM_Threshold)1971 void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold)
1972 {
1973 /* Check the parameters */
1974 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
1975 assert_param(IS_DFSDM_Threshold(DFSDM_Threshold));
1976 assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
1977
1978 if ((DFSDMx->FLTAWSR & ((DFSDM_AWDChannelx >> 16) << DFSDM_Threshold) ) != RESET)
1979 {
1980 /* Clear the pending Flag Bit */
1981 DFSDMx->FLTAWCFR |= (DFSDM_AWDChannelx >> 16) << DFSDM_Threshold;
1982 }
1983 }
1984
1985 /**
1986 * @brief Check whether the specified DFSDM interrupt has occurred or not.
1987 * @param DFSDMx: specifies the filter to be selected :
1988 * This parameter can be one of the following values :
1989 * @arg DFSDM1_0 : DFSDM 1 Filter 0
1990 * @arg DFSDM1_1 : DFSDM 1 Filter 1
1991 * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
1992 * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
1993 * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
1994 * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
1995 * @param DFSDM_IT: specifies the DFSDM interrupt source to check.
1996 * @arg DFSDM_IT_JEOC: End of injected conversion Interrupt source
1997 * @arg DFSDM_IT_REOC: End of regular conversion Interrupt source
1998 * @arg DFSDM_IT_JOVR: Injected data overrun Interrupt source
1999 * @arg DFSDM_IT_ROVR: Regular data overrun Interrupt source
2000 * @arg DFSDM_IT_AWD : Analog watchdog Interrupt source
2001 * @retval The new state of DFSDM_IT (SET or RESET).
2002 */
DFSDM_GetITStatus(DFSDM_Filter_TypeDef * DFSDMx,uint32_t DFSDM_IT)2003 ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT)
2004 {
2005 ITStatus bitstatus = RESET;
2006 uint32_t itstatus = 0x0, itenable = 0x0;
2007
2008 /* Check the parameters */
2009 assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
2010 assert_param(IS_DFSDM_IT(DFSDM_IT));
2011
2012 /* Get the Interrupt Status bit value */
2013 itstatus = DFSDMx->FLTISR & DFSDM_IT;
2014
2015 /* Check if the Interrupt is enabled */
2016 itenable = DFSDMx->FLTCR2 & DFSDM_IT;
2017
2018 if ((itstatus != RESET) && (itenable != RESET))
2019 {
2020 bitstatus = SET;
2021 }
2022 else
2023 {
2024 bitstatus = RESET;
2025 }
2026 return bitstatus;
2027 }
2028
2029 #if defined(STM32F412xG)
2030 /**
2031 * @brief Check whether the specified Clock Absence channel interrupt has occurred or not.
2032 * @param DFSDM_IT_CLKAbsence: specifies on which channel check the interrupt source.
2033 * This parameter can be a value of @ref DFSDM_Clock_Absence_Interrupt_Definition.
2034 * @retval The new state of DFSDM_IT (SET or RESET).
2035 * @note Clock absence interrupt is handled only by DFSDM0.
2036 */
DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence)2037 ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence)
2038 {
2039 ITStatus bitstatus = RESET;
2040 uint32_t itstatus = 0x0, itenable = 0x0;
2041
2042 /* Check the parameters */
2043 assert_param(IS_DFSDM_CLK_ABS_IT(DFSDM_IT_CLKAbsence));
2044
2045 /* Get the Interrupt Status bit value */
2046 itstatus = DFSDM0->FLTISR & DFSDM_IT_CLKAbsence;
2047
2048 /* Check if the Interrupt is enabled */
2049 itenable = DFSDM0->FLTCR2 & DFSDM_IT_CKAB;
2050
2051 if ((itstatus != RESET) && (itenable != RESET))
2052 {
2053 bitstatus = SET;
2054 }
2055 else
2056 {
2057 bitstatus = RESET;
2058 }
2059 return bitstatus;
2060 }
2061
2062 /**
2063 * @brief Check whether the specified Short Circuit channel interrupt has occurred or not.
2064 * @param DFSDM_IT_SCR: specifies on which channel check the interrupt source.
2065 * This parameter can be a value of @ref DFSDM_SCD_Interrupt_Definition.
2066 * @retval The new state of DFSDM_IT (SET or RESET).
2067 * @note Short circuit interrupt is handled only by DFSDM0.
2068 */
DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR)2069 ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR)
2070 {
2071 ITStatus bitstatus = RESET;
2072 uint32_t itstatus = 0x0, itenable = 0x0;
2073
2074 /* Check the parameters */
2075 assert_param(IS_DFSDM_SCD_IT(DFSDM_IT_SCR));
2076
2077 /* Get the Interrupt Status bit value */
2078 itstatus = DFSDM0->FLTISR & DFSDM_IT_SCR;
2079
2080 /* Check if the Interrupt is enabled */
2081 itenable = DFSDM0->FLTCR2 & DFSDM_IT_SCD;
2082
2083 if ((itstatus != RESET) && (itenable != RESET))
2084 {
2085 bitstatus = SET;
2086 }
2087 else
2088 {
2089 bitstatus = RESET;
2090 }
2091 return bitstatus;
2092 }
2093 #endif /* STM32F412xG */
2094
2095 #if defined(STM32F413_423xx)
2096 /**
2097 * @brief Check whether the specified Clock Absence channel interrupt has occurred or not.
2098 * @param Instance: select the instance of DFSDM
2099 * This parameter can be: 1 or 2.
2100 * @param DFSDM_IT_CLKAbsence: specifies on which channel check the interrupt source.
2101 * This parameter can be a value of @ref DFSDM_Clock_Absence_Interrupt_Definition.
2102 * @retval The new state of DFSDM_IT (SET or RESET).
2103 * @note Clock absence interrupt is handled only by DFSDM0.
2104 */
DFSDM_GetClockAbsenceITStatus(uint32_t Instance,uint32_t DFSDM_IT_CLKAbsence)2105 ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence)
2106 {
2107 ITStatus bitstatus = RESET;
2108 uint32_t itstatus = 0x0, itenable = 0x0;
2109
2110 /* Check the parameters */
2111 assert_param(IS_DFSDM_CLK_ABS_IT(DFSDM_IT_CLKAbsence));
2112
2113 if(Instance == 1)
2114 {
2115 /* Get the Interrupt Status bit value */
2116 itstatus = DFSDM1_0->FLTISR & DFSDM_IT_CLKAbsence;
2117 /* Check if the Interrupt is enabled */
2118 itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_CKAB;
2119 }
2120 else
2121 {
2122 /* Get the Interrupt Status bit value */
2123 itstatus = DFSDM2_0->FLTISR & DFSDM_IT_CLKAbsence;
2124 /* Check if the Interrupt is enabled */
2125 itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_CKAB;
2126 }
2127
2128 if ((itstatus != RESET) && (itenable != RESET))
2129 {
2130 bitstatus = SET;
2131 }
2132 else
2133 {
2134 bitstatus = RESET;
2135 }
2136 return bitstatus;
2137 }
2138
2139 /**
2140 * @brief Check whether the specified Short Circuit channel interrupt has occurred or not.
2141 * @param Instance: select the instance of DFSDM
2142 * This parameter can be: 1 or 2.
2143 * @param DFSDM_IT_SCR: specifies on which channel check the interrupt source.
2144 * This parameter can be a value of @ref DFSDM_SCD_Interrupt_Definition.
2145 * @retval The new state of DFSDM_IT (SET or RESET).
2146 * @note Short circuit interrupt is handled only by Filter 0.
2147 */
DFSDM_GetShortCircuitITStatus(uint32_t Instance,uint32_t DFSDM_IT_SCR)2148 ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR)
2149 {
2150 ITStatus bitstatus = RESET;
2151 uint32_t itstatus = 0x0, itenable = 0x0;
2152
2153 /* Check the parameters */
2154 assert_param(IS_DFSDM_SCD_IT(DFSDM_IT_SCR));
2155
2156 if(Instance == 1)
2157 {
2158 /* Get the Interrupt Status bit value */
2159 itstatus = DFSDM1_0->FLTISR & DFSDM_IT_SCR;
2160
2161 /* Check if the Interrupt is enabled */
2162 itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_SCD;
2163 }
2164 else /* DFSDM2 */
2165 {
2166 /* Get the Interrupt Status bit value */
2167 itstatus = DFSDM2_0->FLTISR & DFSDM_IT_SCR;
2168
2169 /* Check if the Interrupt is enabled */
2170 itenable = DFSDM2_0->FLTCR2 & DFSDM_IT_SCD;
2171 }
2172
2173 if ((itstatus != RESET) && (itenable != RESET))
2174 {
2175 bitstatus = SET;
2176 }
2177 else
2178 {
2179 bitstatus = RESET;
2180 }
2181 return bitstatus;
2182 }
2183
2184 #endif /* STM32F413_423xx */
2185 /**
2186 * @}
2187 */
2188
2189 /**
2190 * @}
2191 */
2192 #endif /* STM32F412xG || STM32F413_423xx */
2193
2194 /**
2195 * @}
2196 */
2197
2198 /**
2199 * @}
2200 */
2201
2202