1 /* Copyright Statement: 2 * 3 * This software/firmware and related documentation ("MediaTek Software") are 4 * protected under relevant copyright laws. The information contained herein 5 * is confidential and proprietary to MediaTek Inc. and/or its licensors. 6 * Without the prior written permission of MediaTek inc. and/or its licensors, 7 * any reproduction, modification, use or disclosure of MediaTek Software, 8 * and information contained herein, in whole or in part, shall be strictly prohibited. 9 */ 10 /* MediaTek Inc. (C) 2010. All rights reserved. 11 * 12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES 13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") 14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON 15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. 18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE 19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR 20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH 21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES 22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES 23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK 24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR 25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND 26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, 27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, 28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO 29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 30 * 31 * The following software/firmware and/or related documentation ("MediaTek Software") 32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's 33 * applicable license agreements with MediaTek Inc. 34 */ 35 #pragma once 36 37 #define GIC_CPU_CTRL 0x00 38 #define GIC_CPU_PRIMASK 0x04 39 #define GIC_CPU_BINPOINT 0x08 40 #define GIC_CPU_INTACK 0x0c 41 #define GIC_CPU_EOI 0x10 42 #define GIC_CPU_RUNNINGPRI 0x14 43 #define GIC_CPU_HIGHPRI 0x18 44 45 #define GIC_DIST_CTRL 0x000 46 #define GIC_DIST_CTR 0x004 47 #define GIC_DIST_ENABLE_SET 0x100 48 #define GIC_DIST_ENABLE_CLEAR 0x180 49 #define GIC_DIST_PENDING_SET 0x200 50 #define GIC_DIST_PENDING_CLEAR 0x280 51 #define GIC_DIST_ACTIVE_BIT 0x300 52 #define GIC_DIST_PRI 0x400 53 #define GIC_DIST_TARGET 0x800 54 #define GIC_DIST_CONFIG 0xc00 55 #define GIC_DIST_SOFTINT 0xf00 56 #define GIC_DIST_ICDISR 0x80 57 enum {IRQ_MASK_HEADER = 0xF1F1F1F1, IRQ_MASK_FOOTER = 0xF2F2F2F2}; 58 59 struct mtk_irq_mask { 60 unsigned int header; /* for error checking */ 61 unsigned int mask0; 62 unsigned int mask1; 63 unsigned int mask2; 64 unsigned int mask3; 65 unsigned int mask4; 66 unsigned int mask5; 67 unsigned int mask6; 68 unsigned int mask7; 69 unsigned int footer; /* for error checking */ 70 }; 71 72 73 /* 74 * Define hadware registers. 75 */ 76 77 /* 78 * Define IRQ code. 79 */ 80 81 #define GIC_PRIVATE_SIGNALS (32) 82 83 #define GIC_PPI_OFFSET (27) 84 #define GIC_PPI_GLOBAL_TIMER (GIC_PPI_OFFSET + 0) 85 #define GIC_PPI_LEGACY_FIQ (GIC_PPI_OFFSET + 1) 86 #define GIC_PPI_PRIVATE_TIMER (GIC_PPI_OFFSET + 2) 87 #define GIC_PPI_WATCHDOG_TIMER (GIC_PPI_OFFSET + 3) 88 #define GIC_PPI_LEGACY_IRQ (GIC_PPI_OFFSET + 4) 89 90 91 #define MT_GPT_IRQ_ID 184 92 #define MT_USB0_IRQ_ID 104 93 #define MT_MSDC0_IRQ_ID 111 94 #define MT_MSDC1_IRQ_ID 112 95 96 #define MT_NR_PPI (5) 97 #define MT_NR_SPI (221) 98 #define NR_IRQ_LINE (GIC_PPI_OFFSET + MT_NR_PPI + MT_NR_SPI) // 5 PPIs and 224 SPIs 99 100 #define MT65xx_EDGE_SENSITIVE 0 101 #define MT65xx_LEVEL_SENSITIVE 1 102 103 #define MT65xx_POLARITY_LOW 0 104 #define MT65xx_POLARITY_HIGH 1 105 106 107 int mt_irq_mask_all(struct mtk_irq_mask *mask); //(This is ONLY used for the sleep driver) 108 int mt_irq_mask_restore(struct mtk_irq_mask *mask); //(This is ONLY used for the sleep driver) 109 void mt_irq_set_sens(unsigned int irq, unsigned int sens); 110 void mt_irq_set_polarity(unsigned int irq, unsigned int polarity); 111 int mt_irq_mask_restore(struct mtk_irq_mask *mask); 112 void mt_irq_unmask(unsigned int irq); 113 void mt_irq_ack(unsigned int irq); 114 115 void platform_init_interrupts(void); 116 117