1 /*
2 * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_DPPI_H__
33 #define NRF_DPPI_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_dppi_hal DPPI Controller HAL
43 * @{
44 * @ingroup nrf_dppi
45 * @brief Hardware access layer for managing the Distributed Programmable Peripheral
46 * Interconnect Controller (DPPIC).
47 */
48
49 /** @brief DPPI channel groups. */
50 typedef enum
51 {
52 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
53 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
54 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
55 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
56 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
57 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
58 } nrf_dppi_channel_group_t;
59
60 /** @brief DPPI tasks. */
61 typedef enum
62 {
63 NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
64 NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
65 NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
66 NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
67 NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
68 NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
69 NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
70 NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
71 NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
72 NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
73 NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
74 NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
75 } nrf_dppi_task_t;
76
77 /**
78 * @brief Function for activating a DPPI task.
79 *
80 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
81 * @param[in] dppi_task Task to be activated.
82 */
83 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
84
85 /**
86 * @brief Function for getting the address of the specified DPPI task register.
87 *
88 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
89 * @param[in] task Requested task.
90 *
91 * @return Address of the specified task register.
92 */
93 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
94 nrf_dppi_task_t task);
95
96 /**
97 * @brief Function for checking the state of a specific DPPI channel.
98 *
99 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
100 * @param[in] channel Channel to be checked.
101 *
102 * @retval true The channel is enabled.
103 * @retval false The channel is not enabled.
104 */
105 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
106
107 /**
108 * @brief Function for enabling multiple DPPI channels.
109 *
110 * The bits in @c mask value correspond to particular channels. It means that
111 * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
112 *
113 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
114 * @param[in] mask Channel mask.
115 */
116 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
117
118 /**
119 * @brief Function for disabling multiple DPPI channels.
120 *
121 * The bits in @c mask value correspond to particular channels. It means that
122 * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
123 *
124 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
125 * @param[in] mask Channel mask.
126 */
127 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
128
129 /**
130 * @brief Function for disabling all DPPI channels.
131 *
132 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
133 */
134 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
135
136 /**
137 * @brief Function for setting the subscribe configuration for a given
138 * DPPI task.
139 *
140 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
141 * @param[in] task Task for which to set the configuration.
142 * @param[in] channel Channel through which to subscribe events.
143 */
144 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
145 nrf_dppi_task_t task,
146 uint8_t channel);
147
148 /**
149 * @brief Function for clearing the subscribe configuration for a given
150 * DPPI task.
151 *
152 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
153 * @param[in] task Task for which to clear the configuration.
154 */
155 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
156
157 /**
158 * @brief Function for including multiple DPPI channels in a channel group.
159 *
160 * @details This function adds all specified channels to the group.
161 * The bits in @p channel_mask value correspond to particular channels. It means that
162 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
163 *
164 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
165 * @param[in] channel_mask Channels to be included in the group.
166 * @param[in] channel_group Channel group.
167 */
168 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
169 uint32_t channel_mask,
170 nrf_dppi_channel_group_t channel_group);
171
172 /**
173 * @brief Function for removing multiple DPPI channels from a channel group.
174 *
175 * @details This function removes all specified channels from the group.
176 * The bits in @c channel_mask value correspond to particular channels. It means that
177 * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
178 *
179 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
180 * @param[in] channel_mask Channels to be removed from the group.
181 * @param[in] channel_group Channel group.
182 */
183 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
184 uint32_t channel_mask,
185 nrf_dppi_channel_group_t channel_group);
186
187 /**
188 * @brief Function for removing all DPPI channels from a channel group.
189 *
190 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
191 * @param[in] group Channel group.
192 */
193 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
194 nrf_dppi_channel_group_t group);
195
196 /**
197 * @brief Function for enabling a channel group.
198 *
199 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
200 * @param[in] group Channel group.
201 */
202 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
203 nrf_dppi_channel_group_t group);
204
205 /**
206 * @brief Function for disabling a channel group.
207 *
208 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
209 * @param[in] group Channel group.
210 */
211 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
212 nrf_dppi_channel_group_t group);
213
214 /**
215 * @brief Function for getting the ENABLE task associated with the specified channel group.
216 *
217 * @param[in] index Channel group index.
218 *
219 * @return Requested ENABLE task.
220 */
221 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
222
223 /**
224 * @brief Function for getting the DISABLE task associated with the specified channel group.
225 *
226 * @param[in] index Channel group index.
227 *
228 * @return Requested DISABLE task.
229 */
230 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
231
232 #ifndef NRF_DECLARE_ONLY
233
nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t dppi_task)234 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
235 {
236 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
237 }
238
nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,nrf_dppi_task_t task)239 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
240 nrf_dppi_task_t task)
241 {
242 return (uint32_t) ((uint8_t *) p_reg + (uint32_t ) task);
243 }
244
nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg,uint8_t channel)245 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
246 {
247 NRFX_ASSERT(channel < DPPI_CH_NUM);
248 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
249 }
250
nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)251 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
252 {
253 p_reg->CHENCLR = 0xFFFFFFFFuL;
254 }
255
nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg,uint32_t mask)256 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
257 {
258 p_reg->CHENSET = mask;
259 }
260
nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg,uint32_t mask)261 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
262 {
263 p_reg->CHENCLR = mask;
264 }
265
nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task,uint8_t channel)266 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
267 nrf_dppi_task_t task,
268 uint8_t channel)
269 {
270 NRFX_ASSERT(channel < DPPI_CH_NUM);
271 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
272 ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
273 }
274
nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task)275 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
276 {
277 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
278 }
279
nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)280 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
281 uint32_t channel_mask,
282 nrf_dppi_channel_group_t channel_group)
283 {
284 p_reg->CHG[(uint32_t) channel_group] =
285 p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
286 }
287
nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)288 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
289 uint32_t channel_mask,
290 nrf_dppi_channel_group_t channel_group)
291 {
292 p_reg->CHG[(uint32_t) channel_group] =
293 p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
294 }
295
nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)296 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
297 nrf_dppi_channel_group_t group)
298 {
299 p_reg->CHG[(uint32_t) group] = 0;
300 }
301
nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)302 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
303 {
304 p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
305 }
306
nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)307 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
308 nrf_dppi_channel_group_t group)
309 {
310 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
311 }
312
nrf_dppi_group_enable_task_get(uint8_t index)313 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
314 {
315 NRFX_ASSERT(index < DPPI_GROUP_NUM);
316 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
317 }
318
nrf_dppi_group_disable_task_get(uint8_t index)319 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
320 {
321 NRFX_ASSERT(index < DPPI_GROUP_NUM);
322 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
323 }
324
325 #endif // NRF_DECLARE_ONLY
326
327 /** @} */
328
329 #ifdef __cplusplus
330 }
331 #endif
332
333 #endif // NRF_DPPIC_H__
334