1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_PWM_H__
33 #define NRF_PWM_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_pwm_hal PWM HAL
43 * @{
44 * @ingroup nrf_pwm
45 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
46 */
47
48 /**
49 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
50 * function call to specify that a given output channel shall not be
51 * connected to a physical pin.
52 */
53 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
54
55 /** @brief Number of channels in each PWM instance. */
56 #define NRF_PWM_CHANNEL_COUNT 4
57
58 /**
59 * @brief Helper macro for calculating the number of 16-bit values in the specified
60 * array of duty cycle values.
61 */
62 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
63
64
65 /** @brief PWM tasks. */
66 typedef enum
67 {
68 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
69 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
70 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
71 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
72 } nrf_pwm_task_t;
73
74 /** @brief PWM events. */
75 typedef enum
76 {
77 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
78 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
79 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
80 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
81 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
82 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
83 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
84 } nrf_pwm_event_t;
85
86 /** @brief PWM interrupts. */
87 typedef enum
88 {
89 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
90 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
91 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
92 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
93 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
94 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
95 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
96 } nrf_pwm_int_mask_t;
97
98 /** @brief PWM shortcuts. */
99 typedef enum
100 {
101 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
102 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
103 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
104 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
105 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
106 } nrf_pwm_short_mask_t;
107
108 /** @brief PWM modes of operation. */
109 typedef enum
110 {
111 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
112 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
113 } nrf_pwm_mode_t;
114
115 /** @brief PWM base clock frequencies. */
116 typedef enum
117 {
118 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
119 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
120 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
121 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
122 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
123 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
124 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
125 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
126 } nrf_pwm_clk_t;
127
128 /**
129 * @brief PWM decoder load modes.
130 *
131 * The selected mode determines how the sequence data is read from RAM and
132 * spread to the compare registers.
133 */
134 typedef enum
135 {
136 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
137 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
138 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
139 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
140 } nrf_pwm_dec_load_t;
141
142 /**
143 * @brief PWM decoder next step modes.
144 *
145 * The selected mode determines when the next value from the active sequence
146 * is loaded.
147 */
148 typedef enum
149 {
150 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
151 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
152 } nrf_pwm_dec_step_t;
153
154 /**
155 * @brief Type used for defining duty cycle values for a sequence
156 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
157 */
158 typedef uint16_t nrf_pwm_values_common_t;
159
160 /**
161 * @brief Structure for defining duty cycle values for a sequence
162 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
163 */
164 typedef struct {
165 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
166 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
167 } nrf_pwm_values_grouped_t;
168
169 /**
170 * @brief Structure for defining duty cycle values for a sequence
171 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
172 */
173 typedef struct
174 {
175 uint16_t channel_0; ///< Duty cycle value for channel 0.
176 uint16_t channel_1; ///< Duty cycle value for channel 1.
177 uint16_t channel_2; ///< Duty cycle value for channel 2.
178 uint16_t channel_3; ///< Duty cycle value for channel 3.
179 } nrf_pwm_values_individual_t;
180
181 /**
182 * @brief Structure for defining duty cycle values for a sequence
183 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
184 */
185 typedef struct {
186 uint16_t channel_0; ///< Duty cycle value for channel 0.
187 uint16_t channel_1; ///< Duty cycle value for channel 1.
188 uint16_t channel_2; ///< Duty cycle value for channel 2.
189 uint16_t counter_top; ///< Top value for the pulse generator counter.
190 } nrf_pwm_values_wave_form_t;
191
192 /**
193 * @brief Union grouping pointers to arrays of duty cycle values applicable to
194 * various loading modes.
195 */
196 typedef union {
197 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
198 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
199 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
200 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
201 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
202 } nrf_pwm_values_t;
203
204 /**
205 * @brief Structure for defining a sequence of PWM duty cycles.
206 *
207 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
208 * provided duty cycle values are not copied. The @p values pointer is stored
209 * in the internal register of the peripheral, and the values are loaded from RAM
210 * during the sequence playback. Therefore, you must ensure that the values
211 * do not change before and during the sequence playback (for example,
212 * the values cannot be placed in a local variable that is allocated on stack).
213 * If the sequence is played in a loop and the values are to be updated
214 * before the next iteration, it is safe to modify them when the corresponding
215 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
216 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
217 *
218 * @note The @p repeats and @p end_delay values (which are written to the
219 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
220 * respectively) are ignored at the end of a complex sequence
221 * playback, indicated by the LOOPSDONE event.
222 * See the Product Specification for more information.
223 */
224 typedef struct
225 {
226 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
227 /**< This field is defined as an union of pointers
228 * to provide a convenient way to define duty
229 * cycle values in various loading modes
230 * (see @ref nrf_pwm_dec_load_t).
231 * In each value, the most significant bit (15)
232 * determines the polarity of the output and the
233 * others (14-0) compose the 15-bit value to be
234 * compared with the pulse generator counter. */
235 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
236 uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
237 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
238 } nrf_pwm_sequence_t;
239
240
241 /**
242 * @brief Function for activating the specified PWM task.
243 *
244 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
245 * @param[in] task Task to be activated.
246 */
247 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
248 nrf_pwm_task_t task);
249
250 /**
251 * @brief Function for getting the address of the specified PWM task register.
252 *
253 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
254 * @param[in] task PWM task.
255 *
256 * @return Address of the specified task register.
257 */
258 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
259 nrf_pwm_task_t task);
260
261 /**
262 * @brief Function for clearing the specified PWM event.
263 *
264 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
265 * @param[in] event Event to clear.
266 */
267 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
268 nrf_pwm_event_t event);
269
270 /**
271 * @brief Function for retrieving the state of the PWM event.
272 *
273 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
274 * @param[in] event Event to be checked.
275 *
276 * @retval true The event has been generated.
277 * @retval false The event has not been generated.
278 */
279 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
280 nrf_pwm_event_t event);
281
282 /**
283 * @brief Function for getting the address of the specified PWM event register.
284 *
285 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
286 * @param[in] event PWM event.
287 *
288 * @return Address of the specified event register.
289 */
290 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
291 nrf_pwm_event_t event);
292
293 /**
294 * @brief Function for enabling the specified shortcuts.
295 *
296 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
297 * @param[in] mask Mask of shortcuts to be enabled.
298 */
299 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
300 uint32_t mask);
301
302 /**
303 * @brief Function for disabling the specified shortcuts.
304 *
305 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
306 * @param[in] mask Mask of shortcuts to be disabled.
307 */
308 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
309 uint32_t mask);
310
311 /**
312 * @brief Function for setting the configuration of PWM shortcuts.
313 *
314 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
315 * @param[in] mask Shortcuts configuration to be set.
316 */
317 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
318 uint32_t mask);
319
320 /**
321 * @brief Function for enabling specified interrupts.
322 *
323 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
324 * @param[in] mask Mask of interrupts to be enabled.
325 */
326 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
327 uint32_t mask);
328
329 /**
330 * @brief Function for disabling specified interrupts.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] mask Mask of interrupts to be disabled.
334 */
335 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
336 uint32_t mask);
337
338 /**
339 * @brief Function for setting the configuration of PWM interrupts.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] mask Mask of interrupts to be set.
343 */
344 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
345 uint32_t mask);
346
347 /**
348 * @brief Function for checking if the specified interrupts are enabled.
349 *
350 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
351 * @param[in] mask Mask of interrupts to be checked.
352 *
353 * @return Mask of enabled interrupts.
354 */
355 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask);
356
357 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
358 /**
359 * @brief Function for setting the subscribe configuration for a given
360 * PWM task.
361 *
362 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
363 * @param[in] task Task for which to set the configuration.
364 * @param[in] channel Channel through which to subscribe events.
365 */
366 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
367 nrf_pwm_task_t task,
368 uint8_t channel);
369
370 /**
371 * @brief Function for clearing the subscribe configuration for a given
372 * PWM task.
373 *
374 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
375 * @param[in] task Task for which to clear the configuration.
376 */
377 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
378 nrf_pwm_task_t task);
379
380 /**
381 * @brief Function for setting the publish configuration for a given
382 * PWM event.
383 *
384 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
385 * @param[in] event Event for which to set the configuration.
386 * @param[in] channel Channel through which to publish the event.
387 */
388 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
389 nrf_pwm_event_t event,
390 uint8_t channel);
391
392 /**
393 * @brief Function for clearing the publish configuration for a given
394 * PWM event.
395 *
396 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
397 * @param[in] event Event for which to clear the configuration.
398 */
399 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
400 nrf_pwm_event_t event);
401 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
402
403 /**
404 * @brief Function for enabling the PWM peripheral.
405 *
406 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
407 */
408 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
409
410 /**
411 * @brief Function for disabling the PWM peripheral.
412 *
413 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
414 */
415 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
416
417 /**
418 * @brief Function for assigning pins to PWM output channels.
419 *
420 * Usage of all PWM output channels is optional. If a given channel is not
421 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
422 * number.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
426 */
427 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
428 uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
429
430 /**
431 * @brief Function for getting pin selection associated with specified PWM output channel.
432 *
433 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
434 * @param[in] channel PWM output channel.
435 *
436 * @return Pin selection associated with specified PWM output channel.
437 */
438 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
439
440 /**
441 * @brief Function for configuring the PWM peripheral.
442 *
443 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
444 * @param[in] base_clock Base clock frequency.
445 * @param[in] mode Operating mode of the pulse generator counter.
446 * @param[in] top_value Value up to which the pulse generator counter counts.
447 */
448 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
449 nrf_pwm_clk_t base_clock,
450 nrf_pwm_mode_t mode,
451 uint16_t top_value);
452
453 /**
454 * @brief Function for defining a sequence of PWM duty cycles.
455 *
456 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
457 * @param[in] seq_id Identifier of the sequence (0 or 1).
458 * @param[in] p_seq Pointer to the sequence definition.
459 */
460 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
461 uint8_t seq_id,
462 nrf_pwm_sequence_t const * p_seq);
463
464 /**
465 * @brief Function for modifying the pointer to the duty cycle values
466 * in the specified sequence.
467 *
468 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
469 * @param[in] seq_id Identifier of the sequence (0 or 1).
470 * @param[in] p_values Pointer to an array with duty cycle values.
471 */
472 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
473 uint8_t seq_id,
474 uint16_t const * p_values);
475
476 /**
477 * @brief Function for modifying the total number of duty cycle values
478 * in the specified sequence.
479 *
480 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
481 * @param[in] seq_id Identifier of the sequence (0 or 1).
482 * @param[in] length Number of duty cycle values.
483 */
484 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
485 uint8_t seq_id,
486 uint16_t length);
487
488 /**
489 * @brief Function for modifying the additional number of PWM periods spent
490 * on each duty cycle value in the specified sequence.
491 *
492 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
493 * @param[in] seq_id Identifier of the sequence (0 or 1).
494 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
495 */
496 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
497 uint8_t seq_id,
498 uint32_t refresh);
499
500 /**
501 * @brief Function for modifying the additional time added after the sequence
502 * is played.
503 *
504 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
505 * @param[in] seq_id Identifier of the sequence (0 or 1).
506 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
507 */
508 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
509 uint8_t seq_id,
510 uint32_t end_delay);
511
512 /**
513 * @brief Function for setting the mode of loading sequence data from RAM
514 * and advancing the sequence.
515 *
516 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
517 * @param[in] dec_load Mode of loading sequence data from RAM.
518 * @param[in] dec_step Mode of advancing the active sequence.
519 */
520 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
521 nrf_pwm_dec_load_t dec_load,
522 nrf_pwm_dec_step_t dec_step);
523
524 /**
525 * @brief Function for setting the number of times the sequence playback
526 * should be performed.
527 *
528 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
529 * A single sequence can be played back only once.
530 *
531 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
532 * @param[in] loop_count Number of times to perform the sequence playback.
533 */
534 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count);
535
536
537 #ifndef NRF_DECLARE_ONLY
538
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)539 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
540 nrf_pwm_task_t task)
541 {
542 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
543 }
544
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)545 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
546 nrf_pwm_task_t task)
547 {
548 return ((uint32_t)p_reg + (uint32_t)task);
549 }
550
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)551 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
552 nrf_pwm_event_t event)
553 {
554 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
555 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
556 }
557
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)558 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
559 nrf_pwm_event_t event)
560 {
561 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
562 }
563
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)564 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
565 nrf_pwm_event_t event)
566 {
567 return ((uint32_t)p_reg + (uint32_t)event);
568 }
569
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)570 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, uint32_t mask)
571 {
572 p_reg->SHORTS |= mask;
573 }
574
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)575 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, uint32_t mask)
576 {
577 p_reg->SHORTS &= ~(mask);
578 }
579
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)580 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, uint32_t mask)
581 {
582 p_reg->SHORTS = mask;
583 }
584
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)585 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, uint32_t mask)
586 {
587 p_reg->INTENSET = mask;
588 }
589
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)590 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, uint32_t mask)
591 {
592 p_reg->INTENCLR = mask;
593 }
594
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)595 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, uint32_t mask)
596 {
597 p_reg->INTEN = mask;
598 }
599
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)600 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
601 {
602 return p_reg->INTENSET & mask;
603 }
604
605 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)606 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
607 nrf_pwm_task_t task,
608 uint8_t channel)
609 {
610 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
611 ((uint32_t)channel | PWM_SUBSCRIBE_STOP_EN_Msk);
612 }
613
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)614 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
615 nrf_pwm_task_t task)
616 {
617 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
618 }
619
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)620 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
621 nrf_pwm_event_t event,
622 uint8_t channel)
623 {
624 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
625 ((uint32_t)channel | PWM_PUBLISH_STOPPED_EN_Msk);
626 }
627
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)628 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
629 nrf_pwm_event_t event)
630 {
631 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
632 }
633 #endif // defined(DPPI_PRESENT)
634
nrf_pwm_enable(NRF_PWM_Type * p_reg)635 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
636 {
637 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
638 }
639
nrf_pwm_disable(NRF_PWM_Type * p_reg)640 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
641 {
642 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
643 }
644
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])645 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
646 uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
647 {
648 uint8_t i;
649 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
650 {
651 p_reg->PSEL.OUT[i] = out_pins[i];
652 }
653 }
654
nrf_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)655 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
656 {
657 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
658 return p_reg->PSEL.OUT[channel];
659 }
660
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)661 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
662 nrf_pwm_clk_t base_clock,
663 nrf_pwm_mode_t mode,
664 uint16_t top_value)
665 {
666 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
667
668 p_reg->PRESCALER = base_clock;
669 p_reg->MODE = mode;
670 p_reg->COUNTERTOP = top_value;
671 }
672
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)673 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
674 uint8_t seq_id,
675 nrf_pwm_sequence_t const * p_seq)
676 {
677 NRFX_ASSERT(p_seq != NULL);
678
679 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
680 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
681 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
682 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
683 }
684
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)685 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
686 uint8_t seq_id,
687 uint16_t const * p_values)
688 {
689 NRFX_ASSERT(seq_id <= 1);
690 NRFX_ASSERT(p_values != NULL);
691 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
692 }
693
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)694 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
695 uint8_t seq_id,
696 uint16_t length)
697 {
698 NRFX_ASSERT(seq_id <= 1);
699 NRFX_ASSERT(length != 0);
700 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
701 p_reg->SEQ[seq_id].CNT = length;
702 }
703
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)704 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
705 uint8_t seq_id,
706 uint32_t refresh)
707 {
708 NRFX_ASSERT(seq_id <= 1);
709 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
710 p_reg->SEQ[seq_id].REFRESH = refresh;
711 }
712
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)713 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
714 uint8_t seq_id,
715 uint32_t end_delay)
716 {
717 NRFX_ASSERT(seq_id <= 1);
718 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
719 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
720 }
721
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)722 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
723 nrf_pwm_dec_load_t dec_load,
724 nrf_pwm_dec_step_t dec_step)
725 {
726 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
727 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
728 }
729
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)730 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
731 uint16_t loop_count)
732 {
733 p_reg->LOOP = loop_count;
734 }
735
736 #endif // NRF_DECLARE_ONLY
737
738 /** @} */
739
740 #ifdef __cplusplus
741 }
742 #endif
743
744 #endif // NRF_PWM_H__
745
746