1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_rcc.h 4 * @author MCD Application Team 5 * @version V1.8.1 6 * @date 27-January-2022 7 * @brief This file contains all the functions prototypes for the RCC firmware library. 8 ****************************************************************************** 9 * @attention 10 * 11 * Copyright (c) 2016 STMicroelectronics. 12 * All rights reserved. 13 * 14 * This software is licensed under terms that can be found in the LICENSE file 15 * in the root directory of this software component. 16 * If no LICENSE file comes with this software, it is provided AS-IS. 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef __STM32F4xx_RCC_H 23 #define __STM32F4xx_RCC_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f4xx.h" 31 32 /** @addtogroup STM32F4xx_StdPeriph_Driver 33 * @{ 34 */ 35 36 /** @addtogroup RCC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 typedef struct 42 { 43 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ 44 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ 45 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ 46 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ 47 }RCC_ClocksTypeDef; 48 49 /* Exported constants --------------------------------------------------------*/ 50 51 /** @defgroup RCC_Exported_Constants 52 * @{ 53 */ 54 55 /** @defgroup RCC_HSE_configuration 56 * @{ 57 */ 58 #define RCC_HSE_OFF ((uint8_t)0x00) 59 #define RCC_HSE_ON ((uint8_t)0x01) 60 #define RCC_HSE_Bypass ((uint8_t)0x05) 61 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 62 ((HSE) == RCC_HSE_Bypass)) 63 /** 64 * @} 65 */ 66 67 /** @defgroup RCC_LSE_Dual_Mode_Selection 68 * @{ 69 */ 70 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 71 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 72 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ 73 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 74 /** 75 * @} 76 */ 77 78 /** @defgroup RCC_PLLSAIDivR_Factor 79 * @{ 80 */ 81 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) 82 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) 83 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) 84 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) 85 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ 86 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ 87 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ 88 ((VALUE) == RCC_PLLSAIDivR_Div16)) 89 /** 90 * @} 91 */ 92 93 /** @defgroup RCC_PLL_Clock_Source 94 * @{ 95 */ 96 #define RCC_PLLSource_HSI ((uint32_t)0x00000000) 97 #define RCC_PLLSource_HSE ((uint32_t)0x00400000) 98 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ 99 ((SOURCE) == RCC_PLLSource_HSE)) 100 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) 101 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 102 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 103 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) 104 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 105 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 106 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 107 108 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 109 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 110 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) 111 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 112 #if defined(STM32F446xx) 113 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 114 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) 115 #elif defined(STM32F412xG) || defined(STM32F413_423xx) 116 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 117 #else 118 #endif /* STM32F446xx */ 119 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 120 #if defined(STM32F446xx) || defined(STM32F469_479xx) 121 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 122 #endif /* STM32F446xx || STM32F469_479xx */ 123 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 124 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 125 126 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 127 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 128 129 #if defined(STM32F413_423xx) 130 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 131 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 132 #endif /* STM32F413_423xx */ 133 /** 134 * @} 135 */ 136 137 /** @defgroup RCC_System_Clock_Source 138 * @{ 139 */ 140 141 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 142 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 143 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 144 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) 145 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) 146 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 147 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 148 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ 149 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) 150 /* Add legacy definition */ 151 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK 152 #endif /* STM32F446xx */ 153 154 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 155 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 156 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 157 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 158 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 159 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 160 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 161 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ 162 /** 163 * @} 164 */ 165 166 /** @defgroup RCC_AHB_Clock_Source 167 * @{ 168 */ 169 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 170 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 171 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 172 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 173 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 174 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 175 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 176 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 177 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 178 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 179 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 180 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 181 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 182 ((HCLK) == RCC_SYSCLK_Div512)) 183 /** 184 * @} 185 */ 186 187 /** @defgroup RCC_APB1_APB2_Clock_Source 188 * @{ 189 */ 190 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 191 #define RCC_HCLK_Div2 ((uint32_t)0x00001000) 192 #define RCC_HCLK_Div4 ((uint32_t)0x00001400) 193 #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 194 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) 195 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 196 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 197 ((PCLK) == RCC_HCLK_Div16)) 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_Interrupt_Source 203 * @{ 204 */ 205 #define RCC_IT_LSIRDY ((uint8_t)0x01) 206 #define RCC_IT_LSERDY ((uint8_t)0x02) 207 #define RCC_IT_HSIRDY ((uint8_t)0x04) 208 #define RCC_IT_HSERDY ((uint8_t)0x08) 209 #define RCC_IT_PLLRDY ((uint8_t)0x10) 210 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 211 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 212 #define RCC_IT_CSS ((uint8_t)0x80) 213 214 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 215 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 216 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 217 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 218 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) 219 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) 220 221 /** 222 * @} 223 */ 224 225 /** @defgroup RCC_LSE_Configuration 226 * @{ 227 */ 228 #define RCC_LSE_OFF ((uint8_t)0x00) 229 #define RCC_LSE_ON ((uint8_t)0x01) 230 #define RCC_LSE_Bypass ((uint8_t)0x04) 231 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 232 ((LSE) == RCC_LSE_Bypass)) 233 /** 234 * @} 235 */ 236 237 /** @defgroup RCC_RTC_Clock_Source 238 * @{ 239 */ 240 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 241 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 242 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) 243 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 244 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 245 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) 246 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 247 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) 248 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) 249 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) 250 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) 251 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) 252 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 253 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) 254 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) 255 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) 256 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 257 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) 258 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 259 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) 260 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) 261 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) 262 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 263 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 264 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 265 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) 266 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 267 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) 268 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) 269 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) 270 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) 271 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) 272 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 273 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 274 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ 275 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ 276 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ 277 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ 278 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 279 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 280 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ 281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ 282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ 283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ 284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ 285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ 286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ 289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ 290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ 294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ 295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ 297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ 298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ 299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ 301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ 302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ 303 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) 304 /** 305 * @} 306 */ 307 308 #if defined(STM32F410xx) || defined(STM32F413_423xx) 309 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 310 * @{ 311 */ 312 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) 313 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 314 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 315 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 316 317 #define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ 318 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 319 /* Legacy Defines */ 320 #define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE 321 322 #if defined(STM32F410xx) 323 /** 324 * @} 325 */ 326 327 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 328 * @{ 329 */ 330 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) 331 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 332 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 333 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \ 334 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 335 /** 336 * @} 337 */ 338 #endif /* STM32F413_423xx */ 339 #endif /* STM32F410xx || STM32F413_423xx */ 340 341 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 342 /** @defgroup RCC_I2S_Clock_Source 343 * @{ 344 */ 345 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) 346 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 347 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 348 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) 349 350 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ 351 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCC_I2S_APBBus 357 * @{ 358 */ 359 #define RCC_I2SBus_APB1 ((uint8_t)0x00) 360 #define RCC_I2SBus_APB2 ((uint8_t)0x01) 361 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) 362 /** 363 * @} 364 */ 365 #if defined(STM32F446xx) 366 /** @defgroup RCC_SAI_Clock_Source 367 * @{ 368 */ 369 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) 370 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 371 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 372 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) 373 374 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ 375 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) 376 /** 377 * @} 378 */ 379 380 /** @defgroup RCC_SAI_Instance 381 * @{ 382 */ 383 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00) 384 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01) 385 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) 386 /** 387 * @} 388 */ 389 #endif /* STM32F446xx */ 390 #if defined(STM32F413_423xx) 391 392 /** @defgroup RCC_SAI_BlockA_Clock_Source 393 * @{ 394 */ 395 #define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000) 396 #define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 397 #define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 398 #define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 399 400 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \ 401 ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE)) 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCC_SAI_BlockB_Clock_Source 407 * @{ 408 */ 409 #define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000) 410 #define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 411 #define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 412 #define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 413 414 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \ 415 ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE)) 416 /** 417 * @} 418 */ 419 #endif /* STM32F413_423xx */ 420 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 421 422 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 423 /** @defgroup RCC_I2S_Clock_Source 424 * @{ 425 */ 426 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) 427 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 428 429 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCC_SAI_BlockA_Clock_Source 435 * @{ 436 */ 437 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) 438 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) 439 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) 440 441 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ 442 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ 443 ((SOURCE) == RCC_SAIACLKSource_Ext)) 444 /** 445 * @} 446 */ 447 448 /** @defgroup RCC_SAI_BlockB_Clock_Source 449 * @{ 450 */ 451 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) 452 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) 453 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) 454 455 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ 456 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ 457 ((SOURCE) == RCC_SAIBCLKSource_Ext)) 458 /** 459 * @} 460 */ 461 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ 462 463 /** @defgroup RCC_TIM_PRescaler_Selection 464 * @{ 465 */ 466 #define RCC_TIMPrescDesactivated ((uint8_t)0x00) 467 #define RCC_TIMPrescActivated ((uint8_t)0x01) 468 469 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) 470 /** 471 * @} 472 */ 473 474 #if defined(STM32F469_479xx) 475 /** @defgroup RCC_DSI_Clock_Source_Selection 476 * @{ 477 */ 478 #define RCC_DSICLKSource_PHY ((uint8_t)0x00) 479 #define RCC_DSICLKSource_PLLR ((uint8_t)0x01) 480 #define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \ 481 ((CLKSOURCE) == RCC_DSICLKSource_PLLR)) 482 /** 483 * @} 484 */ 485 #endif /* STM32F469_479xx */ 486 487 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 488 /** @defgroup RCC_SDIO_Clock_Source_Selection 489 * @{ 490 */ 491 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) 492 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) 493 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ 494 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) 495 /** 496 * @} 497 */ 498 499 500 /** @defgroup RCC_48MHZ_Clock_Source_Selection 501 * @{ 502 */ 503 #if defined(STM32F446xx) || defined(STM32F469_479xx) 504 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) 505 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) 506 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ 507 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) 508 #endif /* STM32F446xx || STM32F469_479xx */ 509 #if defined(STM32F412xG) || defined(STM32F413_423xx) 510 #define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00) 511 #define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */ 512 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \ 513 ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ)) 514 #endif /* STM32F412xG || STM32F413_423xx */ 515 /** 516 * @} 517 */ 518 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 519 520 #if defined(STM32F446xx) 521 /** @defgroup RCC_SPDIFRX_Clock_Source_Selection 522 * @{ 523 */ 524 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) 525 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) 526 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ 527 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) 528 /** 529 * @} 530 */ 531 532 /** @defgroup RCC_CEC_Clock_Source_Selection 533 * @{ 534 */ 535 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) 536 #define RCC_CECCLKSource_LSE ((uint8_t)0x01) 537 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ 538 ((CLKSOURCE) == RCC_CECCLKSource_LSE)) 539 /** 540 * @} 541 */ 542 543 /** @defgroup RCC_AHB1_ClockGating 544 * @{ 545 */ 546 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) 547 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) 548 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) 549 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) 550 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) 551 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) 552 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) 553 554 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) 555 556 /** 557 * @} 558 */ 559 #endif /* STM32F446xx */ 560 561 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 562 /** @defgroup RCC_FMPI2C1_Clock_Source 563 * @{ 564 */ 565 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) 566 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 567 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 568 569 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ 570 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) 571 /** 572 * @} 573 */ 574 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ 575 576 #if defined(STM32F412xG) || defined(STM32F413_423xx) 577 /** @defgroup RCC_DFSDM_Clock_Source 578 * @{ 579 */ 580 #define RCC_DFSDMCLKSource_APB ((uint8_t)0x00) 581 #define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01) 582 #define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS)) 583 584 /* Legacy Defines */ 585 #define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB 586 #define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS 587 #define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source 593 * @{ 594 */ 595 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) 596 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 597 #define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2)) 598 599 /* Legacy Defines */ 600 #define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE 601 /** 602 * @} 603 */ 604 605 #if defined(STM32F413_423xx) 606 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source 607 * @{ 608 */ 609 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) 610 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 611 #define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2)) 612 /** 613 * @} 614 */ 615 #endif /* STM32F413_423xx */ 616 #endif /* STM32F412xG || STM32F413_423xx */ 617 618 /** @defgroup RCC_AHB1_Peripherals 619 * @{ 620 */ 621 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) 622 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 623 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) 624 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) 625 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) 626 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) 627 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) 628 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) 629 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 630 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) 631 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) 632 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 633 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) 634 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) 635 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) 636 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) 637 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) 638 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) 639 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) 640 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 641 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) 642 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) 643 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) 644 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) 645 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) 646 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) 647 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) 648 #if defined(STM32F410xx) 649 #define RCC_AHB1Periph_RNG ((uint32_t)0x80000000) 650 #endif /* STM32F410xx */ 651 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) 652 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) 653 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) 654 655 /** 656 * @} 657 */ 658 659 /** @defgroup RCC_AHB2_Peripherals 660 * @{ 661 */ 662 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) 663 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) 664 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) 665 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 666 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) 667 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 668 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) 669 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) 670 /** 671 * @} 672 */ 673 674 /** @defgroup RCC_AHB3_Peripherals 675 * @{ 676 */ 677 #if defined(STM32F40_41xxx) 678 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 679 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 680 #endif /* STM32F40_41xxx */ 681 682 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) 683 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 684 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 685 #endif /* STM32F427_437xx || STM32F429_439xx */ 686 687 #if defined(STM32F446xx) || defined(STM32F469_479xx) 688 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 689 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 690 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 691 #endif /* STM32F446xx || STM32F469_479xx */ 692 693 #if defined(STM32F412xG) || defined(STM32F413_423xx) 694 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 695 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 696 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 697 #endif /* STM32F412xG || STM32F413_423xx */ 698 699 /** 700 * @} 701 */ 702 703 /** @defgroup RCC_APB1_Peripherals 704 * @{ 705 */ 706 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 707 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 708 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 709 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 710 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 711 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 712 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 713 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 714 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 715 #if defined(STM32F410xx) || defined(STM32F413_423xx) 716 #define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) 717 #endif /* STM32F410xx || STM32F413_423xx */ 718 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 719 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 720 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 721 #if defined(STM32F446xx) 722 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) 723 #endif /* STM32F446xx */ 724 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 725 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 726 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 727 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 728 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 729 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 730 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) 731 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 732 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) 733 #endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ 734 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 735 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 736 #if defined(STM32F413_423xx) 737 #define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000) 738 #endif /* STM32F413_423xx */ 739 #if defined(STM32F446xx) 740 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000) 741 #endif /* STM32F446xx */ 742 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 743 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 744 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) 745 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) 746 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) 747 /** 748 * @} 749 */ 750 751 /** @defgroup RCC_APB2_Peripherals 752 * @{ 753 */ 754 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 755 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 756 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) 757 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) 758 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 759 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 760 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) 761 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 762 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 763 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 764 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) 765 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 766 #define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000) 767 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) 768 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) 769 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) 770 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) 771 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) 772 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) 773 #if defined(STM32F446xx) || defined(STM32F469_479xx) 774 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) 775 #endif /* STM32F446xx || STM32F469_479xx */ 776 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) 777 #if defined(STM32F469_479xx) 778 #define RCC_APB2Periph_DSI ((uint32_t)0x08000000) 779 #endif /* STM32F469_479xx */ 780 #if defined(STM32F412xG) || defined(STM32F413_423xx) 781 #define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000) 782 #endif /* STM32F412xG || STM32F413_423xx */ 783 #if defined(STM32F413_423xx) 784 #define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000) 785 #define RCC_APB2Periph_UART9 ((uint32_t)0x02000040) 786 #define RCC_APB2Periph_UART10 ((uint32_t)0x00000080) 787 #endif /* STM32F413_423xx */ 788 789 /* Legacy Defines */ 790 #define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1 791 792 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00)) 793 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00)) 794 795 /** 796 * @} 797 */ 798 799 /** @defgroup RCC_MCO1_Clock_Source_Prescaler 800 * @{ 801 */ 802 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) 803 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 804 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 805 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) 806 #define RCC_MCO1Div_1 ((uint32_t)0x00000000) 807 #define RCC_MCO1Div_2 ((uint32_t)0x04000000) 808 #define RCC_MCO1Div_3 ((uint32_t)0x05000000) 809 #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 810 #define RCC_MCO1Div_5 ((uint32_t)0x07000000) 811 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ 812 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 813 814 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ 815 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ 816 ((DIV) == RCC_MCO1Div_5)) 817 /** 818 * @} 819 */ 820 821 /** @defgroup RCC_MCO2_Clock_Source_Prescaler 822 * @{ 823 */ 824 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 825 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) 826 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) 827 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) 828 #define RCC_MCO2Div_1 ((uint32_t)0x00000000) 829 #define RCC_MCO2Div_2 ((uint32_t)0x20000000) 830 #define RCC_MCO2Div_3 ((uint32_t)0x28000000) 831 #define RCC_MCO2Div_4 ((uint32_t)0x30000000) 832 #define RCC_MCO2Div_5 ((uint32_t)0x38000000) 833 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 834 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) 835 836 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ 837 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 838 ((DIV) == RCC_MCO2Div_5)) 839 /** 840 * @} 841 */ 842 843 /** @defgroup RCC_Flag 844 * @{ 845 */ 846 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 847 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 848 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 849 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 850 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) 851 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 852 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 853 #define RCC_FLAG_BORRST ((uint8_t)0x79) 854 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 855 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 856 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 857 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 858 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 859 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 860 861 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 862 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 863 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 864 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 865 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 866 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 867 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) 868 869 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 870 /** 871 * @} 872 */ 873 874 /** 875 * @} 876 */ 877 878 /* Exported macro ------------------------------------------------------------*/ 879 /* Exported functions --------------------------------------------------------*/ 880 881 /* Function used to set the RCC clock configuration to the default reset state */ 882 void RCC_DeInit(void); 883 884 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 885 void RCC_HSEConfig(uint8_t RCC_HSE); 886 ErrorStatus RCC_WaitForHSEStartUp(void); 887 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 888 void RCC_HSICmd(FunctionalState NewState); 889 void RCC_LSEConfig(uint8_t RCC_LSE); 890 void RCC_LSICmd(FunctionalState NewState); 891 892 void RCC_PLLCmd(FunctionalState NewState); 893 894 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 895 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR); 896 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 897 898 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 899 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); 900 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 901 902 void RCC_PLLI2SCmd(FunctionalState NewState); 903 904 #if defined(STM32F40_41xxx) || defined(STM32F401xx) 905 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); 906 #endif /* STM32F40_41xxx || STM32F401xx */ 907 #if defined(STM32F411xE) 908 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); 909 #endif /* STM32F411xE */ 910 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 911 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); 912 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 913 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 914 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR); 915 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 916 917 void RCC_PLLSAICmd(FunctionalState NewState); 918 #if defined(STM32F469_479xx) 919 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR); 920 #endif /* STM32F469_479xx */ 921 #if defined(STM32F446xx) 922 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ); 923 #endif /* STM32F446xx */ 924 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 925 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); 926 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 927 928 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 929 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); 930 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); 931 932 /* System, AHB and APB busses clocks configuration functions ******************/ 933 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 934 uint8_t RCC_GetSYSCLKSource(void); 935 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 936 void RCC_PCLK1Config(uint32_t RCC_HCLK); 937 void RCC_PCLK2Config(uint32_t RCC_HCLK); 938 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 939 940 /* Peripheral clocks configuration functions **********************************/ 941 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 942 void RCC_RTCCLKCmd(FunctionalState NewState); 943 void RCC_BackupResetCmd(FunctionalState NewState); 944 945 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 946 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); 947 #if defined(STM32F446xx) 948 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); 949 #endif /* STM32F446xx */ 950 #if defined(STM32F413_423xx) 951 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); 952 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); 953 #endif /* STM32F413_423xx */ 954 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 955 956 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 957 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 958 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ 959 960 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 961 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); 962 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); 963 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 964 965 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); 966 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); 967 968 #if defined(STM32F413_423xx) 969 void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR); 970 void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR); 971 #endif /* STM32F413_423xx */ 972 973 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); 974 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); 975 976 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 977 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 978 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 979 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 980 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 981 982 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 983 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 984 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 985 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 986 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 987 988 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 989 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 990 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 991 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 992 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 993 994 /* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */ 995 void RCC_LSEModeConfig(uint8_t RCC_Mode); 996 997 /* Features available only for STM32F469_479xx devices */ 998 #if defined(STM32F469_479xx) 999 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource); 1000 #endif /* STM32F469_479xx */ 1001 1002 /* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */ 1003 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 1004 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource); 1005 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource); 1006 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 1007 1008 /* Features available only for STM32F446xx devices */ 1009 #if defined(STM32F446xx) 1010 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState); 1011 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource); 1012 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource); 1013 #endif /* STM32F446xx */ 1014 1015 /* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */ 1016 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 1017 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource); 1018 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ 1019 1020 /* Features available only for STM32F410xx devices */ 1021 #if defined(STM32F410xx) || defined(STM32F413_423xx) 1022 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource); 1023 #if defined(STM32F410xx) 1024 void RCC_MCO1Cmd(FunctionalState NewState); 1025 void RCC_MCO2Cmd(FunctionalState NewState); 1026 #endif /* STM32F410xx */ 1027 #endif /* STM32F410xx || STM32F413_423xx */ 1028 1029 #if defined(STM32F412xG) || defined(STM32F413_423xx) 1030 void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource); 1031 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource); 1032 #if defined(STM32F413_423xx) 1033 void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource); 1034 #endif /* STM32F413_423xx */ 1035 /* Legacy Defines */ 1036 #define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig 1037 #endif /* STM32F412xG || STM32F413_423xx */ 1038 /* Interrupts and flags management functions **********************************/ 1039 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 1040 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 1041 void RCC_ClearFlag(void); 1042 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 1043 void RCC_ClearITPendingBit(uint8_t RCC_IT); 1044 1045 #ifdef __cplusplus 1046 } 1047 #endif 1048 1049 #endif /* __STM32F4xx_RCC_H */ 1050 1051 /** 1052 * @} 1053 */ 1054 1055 /** 1056 * @} 1057 */ 1058 1059