1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_dfsdm.h 4 * @author MCD Application Team 5 * @version V1.8.1 6 * @date 27-January-2022 7 * @brief This file contains all the functions prototypes for the DFSDM 8 * firmware library 9 ****************************************************************************** 10 * @attention 11 * 12 * Copyright (c) 2016 STMicroelectronics. 13 * All rights reserved. 14 * 15 * This software is licensed under terms that can be found in the LICENSE file 16 * in the root directory of this software component. 17 * If no LICENSE file comes with this software, it is provided AS-IS. 18 * 19 ****************************************************************************** 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __STM32F4XX_DFSDM_H 24 #define __STM32F4XX_DFSDM_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #if defined(STM32F412xG) || defined(STM32F413_423xx) 31 /* Includes ------------------------------------------------------------------*/ 32 #include "stm32f4xx.h" 33 34 /** @addtogroup STM32F4xx_StdPeriph_Driver 35 * @{ 36 */ 37 38 /** @addtogroup DFSDM 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 44 /** 45 * @brief DFSDM Transceiver init structure definition 46 */ 47 typedef struct 48 { 49 uint32_t DFSDM_Interface; /*!< Selects the serial interface type and input clock phase. 50 This parameter can be a value of @ref DFSDM_Interface_Selection */ 51 52 uint32_t DFSDM_Clock; /*!< Specifies the clock source for the serial interface transceiver. 53 This parameter can be a value of @ref DFSDM_Clock_Selection */ 54 55 uint32_t DFSDM_Input; /*!< Specifies the Input mode for the serial interface transceiver. 56 This parameter can be a value of @ref DFSDM_Input_Selection */ 57 58 uint32_t DFSDM_Redirection; /*!< Specifies if the channel input is redirected from channel channel (y+1). 59 This parameter can be a value of @ref DFSDM_Redirection_Selection */ 60 61 uint32_t DFSDM_PackingMode; /*!< Specifies the packing mode for the serial interface transceiver. 62 This parameter can be a value of @ref DFSDM_Pack_Selection */ 63 64 uint32_t DFSDM_DataRightShift; /*!< Defines the final data right bit shift. 65 This parameter can be a value between 0 and 31 */ 66 67 uint32_t DFSDM_Offset; /*!< Sets the calibration offset. 68 This parameter can be a value between 0 and 0xFFFFFF */ 69 70 uint32_t DFSDM_CLKAbsenceDetector; /*!< Enables or disables the Clock Absence Detector. 71 This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */ 72 73 uint32_t DFSDM_ShortCircuitDetector; /*!< Enables or disables the Short Circuit Detector. 74 This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */ 75 }DFSDM_TransceiverInitTypeDef; 76 77 /** 78 * @brief DFSDM filter analog parameters structure definition 79 */ 80 typedef struct 81 { 82 uint32_t DFSDM_SincOrder; /*!< Sets the Sinc Filter Order . 83 This parameter can be a value of @ref DFSDM_Sinc_Order */ 84 85 uint32_t DFSDM_FilterOversamplingRatio; /*!< Sets the Sinc Filter Oversampling Ratio. 86 This parameter can be a value between 1 and 1024 */ 87 88 uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio. 89 This parameter can be a value between 1 and 256 */ 90 }DFSDM_FilterInitTypeDef; 91 92 /* Exported constants --------------------------------------------------------*/ 93 /** @defgroup DFSDM_Interface_Selection 94 * @{ 95 */ 96 #define DFSDM_Interface_SPI_RisingEdge ((uint32_t)0x00000000) /*!< DFSDM SPI interface with rising edge to strobe data */ 97 #define DFSDM_Interface_SPI_FallingEdge ((uint32_t)0x00000001) /*!< DFSDM SPI interface with falling edge to strobe data */ 98 #define DFSDM_Interface_Manchester1 ((uint32_t)0x00000002) /*!< DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */ 99 #define DFSDM_Interface_Manchester2 ((uint32_t)0x00000003) /*!< DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */ 100 101 #define IS_DFSDM_INTERFACE(INTERFACE) (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \ 102 ((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \ 103 ((INTERFACE) == DFSDM_Interface_Manchester1) || \ 104 ((INTERFACE) == DFSDM_Interface_Manchester2)) 105 /** 106 * @} 107 */ 108 109 /** @defgroup DFSDM_Clock_Selection 110 * @{ 111 */ 112 #define DFSDM_Clock_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */ 113 #define DFSDM_Clock_Internal ((uint32_t)0x00000004) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */ 114 #define DFSDM_Clock_InternalDiv2_Mode1 ((uint32_t)0x00000008) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2 115 and clock change is on every rising edge of DFSDM_CKOUT output signal */ 116 #define DFSDM_Clock_InternalDiv2_Mode2 ((uint32_t)0x0000000C) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2 117 and clock change is on every falling edge of DFSDM_CKOUT output signal */ 118 119 #define IS_DFSDM_CLOCK(CLOCK) (((CLOCK) == DFSDM_Clock_External) || \ 120 ((CLOCK) == DFSDM_Clock_Internal) || \ 121 ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \ 122 ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2)) 123 /** 124 * @} 125 */ 126 127 /** @defgroup DFSDM_Input_Selection 128 * @{ 129 */ 130 #define DFSDM_Input_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */ 131 #define DFSDM_Input_ADC ((uint32_t)0x00001000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */ 132 #define DFSDM_Input_Internal ((uint32_t)0x00002000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2 133 and clock change is on every rising edge of DFSDM_CKOUT output signal */ 134 135 #define IS_DFSDM_Input_MODE(INPUT) (((INPUT) == DFSDM_Input_External) || \ 136 ((INPUT) == DFSDM_Input_ADC) || \ 137 ((INPUT) == DFSDM_Input_Internal)) 138 /** 139 * @} 140 */ 141 142 /** @defgroup DFSDM_Redirection_Selection 143 * @{ 144 */ 145 #define DFSDM_Redirection_Disabled ((uint32_t)0x00000000) /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */ 146 #define DFSDM_Redirection_Enabled DFSDM_CHCFGR1_CHINSEL /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */ 147 148 #define IS_DFSDM_Redirection_STATE(STATE) (((STATE) == DFSDM_Redirection_Disabled) || \ 149 ((STATE) == DFSDM_Redirection_Enabled)) 150 /** 151 * @} 152 */ 153 154 /** @defgroup DFSDM_Pack_Selection 155 * @{ 156 */ 157 #define DFSDM_PackingMode_Standard ((uint32_t)0x00000000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */ 158 #define DFSDM_PackingMode_Interleaved ((uint32_t)0x00004000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples: 159 - first sample in INDAT0[15:0] - assigned to channel y 160 - second sample INDAT1[15:0] - assigned to channel y */ 161 #define DFSDM_PackingMode_Dual ((uint32_t)0x00008000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples: 162 - first sample INDAT0[15:0] - assigned to channel y 163 - second sample INDAT1[15:0] - assigned to channel (y+1) */ 164 165 #define IS_DFSDM_PACK_MODE(MODE) (((MODE) == DFSDM_PackingMode_Standard) || \ 166 ((MODE) == DFSDM_PackingMode_Interleaved) || \ 167 ((MODE) == DFSDM_PackingMode_Dual)) 168 /** 169 * @} 170 */ 171 172 /** @defgroup DFSDM_Clock_Absence_Detector_state 173 * @{ 174 */ 175 #define DFSDM_CLKAbsenceDetector_Enable DFSDM_CHCFGR1_CKABEN /*!< DFSDM Clock Absence Detector is Enabled */ 176 #define DFSDM_CLKAbsenceDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Clock Absence Detector is Disabled */ 177 178 #define IS_DFSDM_CLK_DETECTOR_STATE(STATE) (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \ 179 ((STATE) == DFSDM_CLKAbsenceDetector_Disable)) 180 /** 181 * @} 182 */ 183 184 /** @defgroup DFSDM_Short_Circuit_Detector_state 185 * @{ 186 */ 187 #define DFSDM_ShortCircuitDetector_Enable DFSDM_CHCFGR1_SCDEN /*!< DFSDM Short Circuit Detector is Enabled */ 188 #define DFSDM_ShortCircuitDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Short Circuit Detector is Disabled */ 189 190 #define IS_DFSDM_SC_DETECTOR_STATE(STATE) (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \ 191 ((STATE) == DFSDM_ShortCircuitDetector_Disable)) 192 /** 193 * @} 194 */ 195 196 /** @defgroup DFSDM_Sinc_Order 197 * @{ 198 */ 199 #define DFSDM_SincOrder_FastSinc ((uint32_t)0x00000000) /*!< DFSDM Sinc filter order = Fast sinc */ 200 #define DFSDM_SincOrder_Sinc1 ((uint32_t)0x20000000) /*!< DFSDM Sinc filter order = 1 */ 201 #define DFSDM_SincOrder_Sinc2 ((uint32_t)0x40000000) /*!< DFSDM Sinc filter order = 2 */ 202 #define DFSDM_SincOrder_Sinc3 ((uint32_t)0x60000000) /*!< DFSDM Sinc filter order = 3 */ 203 #define DFSDM_SincOrder_Sinc4 ((uint32_t)0x80000000) /*!< DFSDM Sinc filter order = 4 */ 204 #define DFSDM_SincOrder_Sinc5 ((uint32_t)0xA0000000) /*!< DFSDM Sinc filter order = 5 */ 205 206 #define IS_DFSDM_SINC_ORDER(ORDER) (((ORDER) == DFSDM_SincOrder_FastSinc) || \ 207 ((ORDER) == DFSDM_SincOrder_Sinc1) || \ 208 ((ORDER) == DFSDM_SincOrder_Sinc2) || \ 209 ((ORDER) == DFSDM_SincOrder_Sinc3) || \ 210 ((ORDER) == DFSDM_SincOrder_Sinc4) || \ 211 ((ORDER) == DFSDM_SincOrder_Sinc5)) 212 /** 213 * @} 214 */ 215 216 /** @defgroup DFSDM_Break_Signal_Assignment 217 * @{ 218 */ 219 #define DFSDM_SCDBreak_0 ((uint32_t)0x00001000) /*!< DFSDM Break 0 signal assigned to short circuit detector */ 220 #define DFSDM_SCDBreak_1 ((uint32_t)0x00002000) /*!< DFSDM Break 1 signal assigned to short circuit detector */ 221 #define DFSDM_SCDBreak_2 ((uint32_t)0x00004000) /*!< DFSDM Break 2 signal assigned to short circuit detector */ 222 #define DFSDM_SCDBreak_3 ((uint32_t)0x00008000) /*!< DFSDM Break 3 signal assigned to short circuit detector */ 223 224 #define IS_DFSDM_SCD_BREAK_SIGNAL(RANK) (((RANK) == DFSDM_SCDBreak_0) || \ 225 ((RANK) == DFSDM_SCDBreak_1) || \ 226 ((RANK) == DFSDM_SCDBreak_2) || \ 227 ((RANK) == DFSDM_SCDBreak_3)) 228 /** 229 * @} 230 */ 231 232 /** @defgroup DFSDM_AWD_Sinc_Order 233 * @{ 234 */ 235 #define DFSDM_AWDSincOrder_Fast ((uint32_t)0x00000000) /*!< DFSDM Fast sinc filter */ 236 #define DFSDM_AWDSincOrder_Sinc1 ((uint32_t)0x00400000) /*!< DFSDM sinc1 filter */ 237 #define DFSDM_AWDSincOrder_Sinc2 ((uint32_t)0x00800000) /*!< DFSDM sinc2 filter */ 238 #define DFSDM_AWDSincOrder_Sinc3 ((uint32_t)0x00C00000) /*!< DFSDM sinc3 filter */ 239 240 #define IS_DFSDM_AWD_SINC_ORDER(ORDER) (((ORDER) == DFSDM_AWDSincOrder_Fast) || \ 241 ((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \ 242 ((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \ 243 ((ORDER) == DFSDM_AWDSincOrder_Sinc3)) 244 /** 245 * @} 246 */ 247 248 /** @defgroup DFSDM_AWD_CHANNEL 249 * @{ 250 */ 251 #define DFSDM_AWDChannel0 ((uint32_t)0x00010000) /*!< DFSDM AWDx guard channel 0 */ 252 #define DFSDM_AWDChannel1 ((uint32_t)0x00020000) /*!< DFSDM AWDx guard channel 1 */ 253 #define DFSDM_AWDChannel2 ((uint32_t)0x00040000) /*!< DFSDM AWDx guard channel 2 */ 254 #define DFSDM_AWDChannel3 ((uint32_t)0x00080000) /*!< DFSDM AWDx guard channel 3 */ 255 #define DFSDM_AWDChannel4 ((uint32_t)0x00100000) /*!< DFSDM AWDx guard channel 4 */ 256 #define DFSDM_AWDChannel5 ((uint32_t)0x00200000) /*!< DFSDM AWDx guard channel 5 */ 257 #define DFSDM_AWDChannel6 ((uint32_t)0x00400000) /*!< DFSDM AWDx guard channel 6 */ 258 #define DFSDM_AWDChannel7 ((uint32_t)0x00800000) /*!< DFSDM AWDx guard channel 7 */ 259 260 #define IS_DFSDM_AWD_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_AWDChannel0) || \ 261 ((CHANNEL) == DFSDM_AWDChannel1) || \ 262 ((CHANNEL) == DFSDM_AWDChannel2) || \ 263 ((CHANNEL) == DFSDM_AWDChannel3) || \ 264 ((CHANNEL) == DFSDM_AWDChannel4) || \ 265 ((CHANNEL) == DFSDM_AWDChannel5) || \ 266 ((CHANNEL) == DFSDM_AWDChannel6) || \ 267 ((CHANNEL) == DFSDM_AWDChannel7)) 268 /** 269 * @} 270 */ 271 272 /** @defgroup DFSDM_Threshold_Selection 273 * @{ 274 */ 275 #define DFSDM_Threshold_Low ((uint8_t)0x00) /*!< DFSDM Low threshold */ 276 #define DFSDM_Threshold_High ((uint8_t)0x08) /*!< DFSDM High threshold */ 277 278 #define IS_DFSDM_Threshold(THR) (((THR) == DFSDM_Threshold_Low) || \ 279 ((THR) == DFSDM_Threshold_High)) 280 /** 281 * @} 282 */ 283 284 /** @defgroup DFSDM_AWD_Fast_Mode_Selection 285 * @{ 286 */ 287 #define DFSDM_AWDFastMode_Disable ((uint32_t)0x00000000) /*!< DFSDM Fast mode for AWD is disabled */ 288 #define DFSDM_AWDFastMode_Enable ((uint32_t)0x40000000) /*!< DFSDM Fast mode for AWD is enabled */ 289 290 #define IS_DFSDM_AWD_MODE(MODE) (((MODE) == DFSDM_AWDFastMode_Disable) || \ 291 ((MODE) == DFSDM_AWDFastMode_Enable)) 292 /** 293 * @} 294 */ 295 296 /** @defgroup DFSDM_Clock_Output_Source_Selection 297 * @{ 298 */ 299 #define DFSDM_ClkOutSource_SysClock ((uint32_t)0x00000000) /*!< DFSDM Source for output clock is comming from system clock */ 300 #define DFSDM_ClkOutSource_AudioClock DFSDM_CHCFGR1_CKOUTSRC /*!< DFSDM Source for output clock is comming from audio clock */ 301 302 #define IS_DFSDM_CLOCK_OUT_SOURCE(SRC) (((SRC) == DFSDM_ClkOutSource_SysClock) || \ 303 ((SRC) == DFSDM_ClkOutSource_AudioClock)) 304 /** 305 * @} 306 */ 307 308 /** @defgroup DFSDM_Conversion_Mode 309 * @{ 310 */ 311 #define DFSDM_DMAConversionMode_Regular ((uint32_t)0x00000010) /*!< DFSDM Regular mode */ 312 #define DFSDM_DMAConversionMode_Injected ((uint32_t)0x00000000) /*!< DFSDM Injected mode */ 313 314 #define IS_DFSDM_CONVERSION_MODE(MODE) (((MODE) == DFSDM_DMAConversionMode_Regular) || \ 315 ((MODE) == DFSDM_DMAConversionMode_Injected)) 316 /** 317 * @} 318 */ 319 320 /** @defgroup DFSDM_Extremes_Channel_Selection 321 * @{ 322 */ 323 #define DFSDM_ExtremChannel0 ((uint32_t)0x00000100) /*!< DFSDM Extreme detector guard channel 0 */ 324 #define DFSDM_ExtremChannel1 ((uint32_t)0x00000200) /*!< DFSDM Extreme detector guard channel 1 */ 325 #define DFSDM_ExtremChannel2 ((uint32_t)0x00000400) /*!< DFSDM Extreme detector guard channel 2 */ 326 #define DFSDM_ExtremChannel3 ((uint32_t)0x00000800) /*!< DFSDM Extreme detector guard channel 3 */ 327 #define DFSDM_ExtremChannel4 ((uint32_t)0x00001000) /*!< DFSDM Extreme detector guard channel 4 */ 328 #define DFSDM_ExtremChannel5 ((uint32_t)0x00002000) /*!< DFSDM Extreme detector guard channel 5 */ 329 #define DFSDM_ExtremChannel6 ((uint32_t)0x00004000) /*!< DFSDM Extreme detector guard channel 6 */ 330 #define DFSDM_ExtremChannel7 ((uint32_t)0x00008000) /*!< DFSDM Extreme detector guard channel 7 */ 331 332 #define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \ 333 ((CHANNEL) == DFSDM_ExtremChannel1) || \ 334 ((CHANNEL) == DFSDM_ExtremChannel2) || \ 335 ((CHANNEL) == DFSDM_ExtremChannel3) || \ 336 ((CHANNEL) == DFSDM_ExtremChannel4) || \ 337 ((CHANNEL) == DFSDM_ExtremChannel5) || \ 338 ((CHANNEL) == DFSDM_ExtremChannel6) || \ 339 ((CHANNEL) == DFSDM_ExtremChannel7)) 340 /** 341 * @} 342 */ 343 344 /** @defgroup DFSDM_Injected_Channel_Selection 345 * @{ 346 */ 347 #define DFSDM_InjectedChannel0 ((uint32_t)0x00000001) /*!< DFSDM channel 0 is selected as injected channel */ 348 #define DFSDM_InjectedChannel1 ((uint32_t)0x00000002) /*!< DFSDM channel 1 is selected as injected channel */ 349 #define DFSDM_InjectedChannel2 ((uint32_t)0x00000004) /*!< DFSDM channel 2 is selected as injected channel */ 350 #define DFSDM_InjectedChannel3 ((uint32_t)0x00000008) /*!< DFSDM channel 3 is selected as injected channel */ 351 #define DFSDM_InjectedChannel4 ((uint32_t)0x00000010) /*!< DFSDM channel 4 is selected as injected channel */ 352 #define DFSDM_InjectedChannel5 ((uint32_t)0x00000020) /*!< DFSDM channel 5 is selected as injected channel */ 353 #define DFSDM_InjectedChannel6 ((uint32_t)0x00000040) /*!< DFSDM channel 6 is selected as injected channel */ 354 #define DFSDM_InjectedChannel7 ((uint32_t)0x00000080) /*!< DFSDM channel 7 is selected as injected channel */ 355 356 #define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \ 357 ((CHANNEL) == DFSDM_InjectedChannel1) || \ 358 ((CHANNEL) == DFSDM_InjectedChannel2) || \ 359 ((CHANNEL) == DFSDM_InjectedChannel3) || \ 360 ((CHANNEL) == DFSDM_InjectedChannel4) || \ 361 ((CHANNEL) == DFSDM_InjectedChannel5) || \ 362 ((CHANNEL) == DFSDM_InjectedChannel6) || \ 363 ((CHANNEL) == DFSDM_InjectedChannel7)) 364 /** 365 * @} 366 */ 367 368 /** @defgroup DFSDM_Regular_Channel_Selection 369 * @{ 370 */ 371 #define DFSDM_RegularChannel0 ((uint32_t)0x00000000) /*!< DFSDM channel 0 is selected as regular channel */ 372 #define DFSDM_RegularChannel1 ((uint32_t)0x01000000) /*!< DFSDM channel 1 is selected as regular channel */ 373 #define DFSDM_RegularChannel2 ((uint32_t)0x02000000) /*!< DFSDM channel 2 is selected as regular channel */ 374 #define DFSDM_RegularChannel3 ((uint32_t)0x03000000) /*!< DFSDM channel 3 is selected as regular channel */ 375 #define DFSDM_RegularChannel4 ((uint32_t)0x04000000) /*!< DFSDM channel 4 is selected as regular channel */ 376 #define DFSDM_RegularChannel5 ((uint32_t)0x05000000) /*!< DFSDM channel 5 is selected as regular channel */ 377 #define DFSDM_RegularChannel6 ((uint32_t)0x06000000) /*!< DFSDM channel 6 is selected as regular channel */ 378 #define DFSDM_RegularChannel7 ((uint32_t)0x07000000) /*!< DFSDM channel 7 is selected as regular channel */ 379 380 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \ 381 ((CHANNEL) == DFSDM_RegularChannel1) || \ 382 ((CHANNEL) == DFSDM_RegularChannel2) || \ 383 ((CHANNEL) == DFSDM_RegularChannel3) || \ 384 ((CHANNEL) == DFSDM_RegularChannel4) || \ 385 ((CHANNEL) == DFSDM_RegularChannel5) || \ 386 ((CHANNEL) == DFSDM_RegularChannel6) || \ 387 ((CHANNEL) == DFSDM_RegularChannel7)) 388 /** 389 * @} 390 */ 391 392 /** @defgroup DFSDM_Injected_Trigger_signal 393 * @{ 394 */ 395 #define DFSDM_Trigger_TIM1_TRGO ((uint32_t)0x00000000) /*!< DFSDM Internal trigger 0 */ 396 #define DFSDM_Trigger_TIM1_TRGO2 ((uint32_t)0x00000100) /*!< DFSDM Internal trigger 1 */ 397 #define DFSDM_Trigger_TIM8_TRGO ((uint32_t)0x00000200) /*!< DFSDM Internal trigger 2 */ 398 #define DFSDM_Trigger_TIM8_TRGO2 ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 3 */ 399 #define DFSDM_Trigger_TIM3_TRGO ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 4 */ 400 #define DFSDM_Trigger_TIM4_TRGO ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 5 */ 401 #define DFSDM_Trigger_TIM16_OC1 ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 6 */ 402 #define DFSDM_Trigger_TIM6_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 7 */ 403 #define DFSDM_Trigger_TIM7_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 8 */ 404 #define DFSDM_Trigger_EXTI11 ((uint32_t)0x00000600) /*!< DFSDM External trigger 0 */ 405 #define DFSDM_Trigger_EXTI15 ((uint32_t)0x00000700) /*!< DFSDM External trigger 1 */ 406 407 #define IS_DFSDM0_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \ 408 ((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \ 409 ((TRIG) == DFSDM_Trigger_TIM8_TRGO) || \ 410 ((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \ 411 ((TRIG) == DFSDM_Trigger_TIM4_TRGO) || \ 412 ((TRIG) == DFSDM_Trigger_TIM6_TRGO) || \ 413 ((TRIG) == DFSDM_Trigger_TIM7_TRGO) || \ 414 ((TRIG) == DFSDM_Trigger_EXTI15) || \ 415 ((TRIG) == DFSDM_Trigger_TIM3_TRGO) || \ 416 ((TRIG) == DFSDM_Trigger_TIM16_OC1) || \ 417 ((TRIG) == DFSDM_Trigger_EXTI11)) 418 419 #define IS_DFSDM1_INJ_TRIGGER(TRIG) IS_DFSDM0_INJ_TRIGGER(TRIG) 420 /** 421 * @} 422 */ 423 424 /** @defgroup DFSDM_Trigger_Edge_selection 425 * @{ 426 */ 427 #define DFSDM_TriggerEdge_Disabled ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */ 428 #define DFSDM_TriggerEdge_Rising ((uint32_t)0x00002000) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */ 429 #define DFSDM_TriggerEdge_Falling ((uint32_t)0x00004000) /*!< DFSDM Each falling edge makes a request to launch an injected conversion */ 430 #define DFSDM_TriggerEdge_BothEdges ((uint32_t)0x00006000) /*!< DFSDM Both edges make a request to launch an injected conversion */ 431 432 #define IS_DFSDM_TRIGGER_EDGE(EDGE) (((EDGE) == DFSDM_TriggerEdge_Disabled) || \ 433 ((EDGE) == DFSDM_TriggerEdge_Rising) || \ 434 ((EDGE) == DFSDM_TriggerEdge_Falling) || \ 435 ((EDGE) == DFSDM_TriggerEdge_BothEdges)) 436 /** 437 * @} 438 */ 439 440 /** @defgroup DFSDM_Injected_Conversion_Mode_Selection 441 * @{ 442 */ 443 #define DFSDM_InjectConvMode_Single ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */ 444 #define DFSDM_InjectConvMode_Scan ((uint32_t)0x00000010) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */ 445 446 #define IS_DFSDM_INJ_CONV_MODE(MODE) (((MODE) == DFSDM_InjectConvMode_Single) || \ 447 ((MODE) == DFSDM_InjectConvMode_Scan)) 448 /** 449 * @} 450 */ 451 452 /** @defgroup DFSDM_Interrupts_Definition 453 * @{ 454 */ 455 #define DFSDM_IT_JEOC DFSDM_FLTCR2_JEOCIE 456 #define DFSDM_IT_REOC DFSDM_FLTCR2_REOCIE 457 #define DFSDM_IT_JOVR DFSDM_FLTCR2_JOVRIE 458 #define DFSDM_IT_ROVR DFSDM_FLTCR2_ROVRIE 459 #define DFSDM_IT_AWD DFSDM_FLTCR2_AWDIE 460 #define DFSDM_IT_SCD DFSDM_FLTCR2_SCDIE 461 #define DFSDM_IT_CKAB DFSDM_FLTCR2_CKABIE 462 463 #define IS_DFSDM_IT(IT) (((IT) == DFSDM_IT_JEOC) || \ 464 ((IT) == DFSDM_IT_REOC) || \ 465 ((IT) == DFSDM_IT_JOVR) || \ 466 ((IT) == DFSDM_IT_ROVR) || \ 467 ((IT) == DFSDM_IT_AWD) || \ 468 ((IT) == DFSDM_IT_SCD) || \ 469 ((IT) == DFSDM_IT_CKAB)) 470 /** 471 * @} 472 */ 473 474 /** @defgroup DFSDM_Flag_Definition 475 * @{ 476 */ 477 #define DFSDM_FLAG_JEOC DFSDM_FLTISR_JEOCF 478 #define DFSDM_FLAG_REOC DFSDM_FLTISR_REOCF 479 #define DFSDM_FLAG_JOVR DFSDM_FLTISR_JOVRF 480 #define DFSDM_FLAG_ROVR DFSDM_FLTISR_ROVRF 481 #define DFSDM_FLAG_AWD DFSDM_FLTISR_AWDF 482 #define DFSDM_FLAG_JCIP DFSDM_FLTISR_JCIP 483 #define DFSDM_FLAG_RCIP DFSDM_FLTISR_RCIP 484 485 #define IS_DFSDM_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_JEOC) || \ 486 ((FLAG) == DFSDM_FLAG_REOC) || \ 487 ((FLAG) == DFSDM_FLAG_JOVR) || \ 488 ((FLAG) == DFSDM_FLAG_ROVR) || \ 489 ((FLAG) == DFSDM_FLAG_AWD) || \ 490 ((FLAG) == DFSDM_FLAG_JCIP) || \ 491 ((FLAG) == DFSDM_FLAG_RCIP)) 492 /** 493 * @} 494 */ 495 496 /** @defgroup DFSDM_Clock_Absence_Flag_Definition 497 * @{ 498 */ 499 #define DFSDM_FLAG_CLKAbsence_Channel0 ((uint32_t)0x00010000) 500 #define DFSDM_FLAG_CLKAbsence_Channel1 ((uint32_t)0x00020000) 501 #define DFSDM_FLAG_CLKAbsence_Channel2 ((uint32_t)0x00040000) 502 #define DFSDM_FLAG_CLKAbsence_Channel3 ((uint32_t)0x00080000) 503 #define DFSDM_FLAG_CLKAbsence_Channel4 ((uint32_t)0x00100000) 504 #define DFSDM_FLAG_CLKAbsence_Channel5 ((uint32_t)0x00200000) 505 #define DFSDM_FLAG_CLKAbsence_Channel6 ((uint32_t)0x00400000) 506 #define DFSDM_FLAG_CLKAbsence_Channel7 ((uint32_t)0x00800000) 507 508 #define IS_DFSDM_CLK_ABS_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \ 509 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \ 510 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \ 511 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \ 512 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \ 513 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \ 514 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \ 515 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7)) 516 /** 517 * @} 518 */ 519 520 /** @defgroup DFSDM_SCD_Flag_Definition 521 * @{ 522 */ 523 #define DFSDM_FLAG_SCD_Channel0 ((uint32_t)0x01000000) 524 #define DFSDM_FLAG_SCD_Channel1 ((uint32_t)0x02000000) 525 #define DFSDM_FLAG_SCD_Channel2 ((uint32_t)0x04000000) 526 #define DFSDM_FLAG_SCD_Channel3 ((uint32_t)0x08000000) 527 #define DFSDM_FLAG_SCD_Channel4 ((uint32_t)0x10000000) 528 #define DFSDM_FLAG_SCD_Channel5 ((uint32_t)0x20000000) 529 #define DFSDM_FLAG_SCD_Channel6 ((uint32_t)0x40000000) 530 #define DFSDM_FLAG_SCD_Channel7 ((uint32_t)0x80000000) 531 532 #define IS_DFSDM_SCD_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \ 533 ((FLAG) == DFSDM_FLAG_SCD_Channel1) || \ 534 ((FLAG) == DFSDM_FLAG_SCD_Channel2) || \ 535 ((FLAG) == DFSDM_FLAG_SCD_Channel3) || \ 536 ((FLAG) == DFSDM_FLAG_SCD_Channel4) || \ 537 ((FLAG) == DFSDM_FLAG_SCD_Channel5) || \ 538 ((FLAG) == DFSDM_FLAG_SCD_Channel6) || \ 539 ((FLAG) == DFSDM_FLAG_SCD_Channel7)) 540 /** 541 * @} 542 */ 543 544 /** @defgroup DFSDM_Clear_Flag_Definition 545 * @{ 546 */ 547 #define DFSDM_CLEARF_JOVR DFSDM_FLTICR_CLRJOVRF 548 #define DFSDM_CLEARF_ROVR DFSDM_FLTICR_CLRROVRF 549 550 #define IS_DFSDM_CLEAR_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_JOVR) || \ 551 ((FLAG) == DFSDM_CLEARF_ROVR)) 552 /** 553 * @} 554 */ 555 556 /** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition 557 * @{ 558 */ 559 #define DFSDM_CLEARF_CLKAbsence_Channel0 ((uint32_t)0x00010000) 560 #define DFSDM_CLEARF_CLKAbsence_Channel1 ((uint32_t)0x00020000) 561 #define DFSDM_CLEARF_CLKAbsence_Channel2 ((uint32_t)0x00040000) 562 #define DFSDM_CLEARF_CLKAbsence_Channel3 ((uint32_t)0x00080000) 563 #define DFSDM_CLEARF_CLKAbsence_Channel4 ((uint32_t)0x00100000) 564 #define DFSDM_CLEARF_CLKAbsence_Channel5 ((uint32_t)0x00200000) 565 #define DFSDM_CLEARF_CLKAbsence_Channel6 ((uint32_t)0x00400000) 566 #define DFSDM_CLEARF_CLKAbsence_Channel7 ((uint32_t)0x00800000) 567 568 #define IS_DFSDM_CLK_ABS_CLEARF(FLAG) (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \ 569 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \ 570 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \ 571 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \ 572 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \ 573 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \ 574 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \ 575 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7)) 576 /** 577 * @} 578 */ 579 580 /** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition 581 * @{ 582 */ 583 #define DFSDM_CLEARF_SCD_Channel0 ((uint32_t)0x01000000) 584 #define DFSDM_CLEARF_SCD_Channel1 ((uint32_t)0x02000000) 585 #define DFSDM_CLEARF_SCD_Channel2 ((uint32_t)0x04000000) 586 #define DFSDM_CLEARF_SCD_Channel3 ((uint32_t)0x08000000) 587 #define DFSDM_CLEARF_SCD_Channel4 ((uint32_t)0x10000000) 588 #define DFSDM_CLEARF_SCD_Channel5 ((uint32_t)0x20000000) 589 #define DFSDM_CLEARF_SCD_Channel6 ((uint32_t)0x40000000) 590 #define DFSDM_CLEARF_SCD_Channel7 ((uint32_t)0x80000000) 591 592 #define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \ 593 ((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \ 594 ((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \ 595 ((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \ 596 ((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \ 597 ((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \ 598 ((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \ 599 ((FLAG) == DFSDM_CLEARF_SCD_Channel7)) 600 /** 601 * @} 602 */ 603 604 /** @defgroup DFSDM_Clock_Absence_Interrupt_Definition 605 * @{ 606 */ 607 #define DFSDM_IT_CLKAbsence_Channel0 ((uint32_t)0x00010000) 608 #define DFSDM_IT_CLKAbsence_Channel1 ((uint32_t)0x00020000) 609 #define DFSDM_IT_CLKAbsence_Channel2 ((uint32_t)0x00040000) 610 #define DFSDM_IT_CLKAbsence_Channel3 ((uint32_t)0x00080000) 611 #define DFSDM_IT_CLKAbsence_Channel4 ((uint32_t)0x00100000) 612 #define DFSDM_IT_CLKAbsence_Channel5 ((uint32_t)0x00200000) 613 #define DFSDM_IT_CLKAbsence_Channel6 ((uint32_t)0x00400000) 614 #define DFSDM_IT_CLKAbsence_Channel7 ((uint32_t)0x00800000) 615 616 #define IS_DFSDM_CLK_ABS_IT(IT) (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \ 617 ((IT) == DFSDM_IT_CLKAbsence_Channel1) || \ 618 ((IT) == DFSDM_IT_CLKAbsence_Channel2) || \ 619 ((IT) == DFSDM_IT_CLKAbsence_Channel3) || \ 620 ((IT) == DFSDM_IT_CLKAbsence_Channel4) || \ 621 ((IT) == DFSDM_IT_CLKAbsence_Channel5) || \ 622 ((IT) == DFSDM_IT_CLKAbsence_Channel6) || \ 623 ((IT) == DFSDM_IT_CLKAbsence_Channel7)) 624 /** 625 * @} 626 */ 627 628 /** @defgroup DFSDM_SCD_Interrupt_Definition 629 * @{ 630 */ 631 #define DFSDM_IT_SCD_Channel0 ((uint32_t)0x01000000) 632 #define DFSDM_IT_SCD_Channel1 ((uint32_t)0x02000000) 633 #define DFSDM_IT_SCD_Channel2 ((uint32_t)0x04000000) 634 #define DFSDM_IT_SCD_Channel3 ((uint32_t)0x08000000) 635 #define DFSDM_IT_SCD_Channel4 ((uint32_t)0x10000000) 636 #define DFSDM_IT_SCD_Channel5 ((uint32_t)0x20000000) 637 #define DFSDM_IT_SCD_Channel6 ((uint32_t)0x40000000) 638 #define DFSDM_IT_SCD_Channel7 ((uint32_t)0x80000000) 639 640 #define IS_DFSDM_SCD_IT(IT) (((IT) == DFSDM_IT_SCD_Channel0) || \ 641 ((IT) == DFSDM_IT_SCD_Channel1) || \ 642 ((IT) == DFSDM_IT_SCD_Channel2) || \ 643 ((IT) == DFSDM_IT_SCD_Channel3) || \ 644 ((IT) == DFSDM_IT_SCD_Channel4) || \ 645 ((IT) == DFSDM_IT_SCD_Channel5) || \ 646 ((IT) == DFSDM_IT_SCD_Channel6) || \ 647 ((IT) == DFSDM_IT_SCD_Channel7)) 648 /** 649 * @} 650 */ 651 652 #define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT) ((SHIFT) < 0x20 ) 653 654 #define IS_DFSDM_OFFSET(OFFSET) ((OFFSET) < 0x01000000 ) 655 656 #if defined(STM32F413_423xx) 657 #define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \ 658 ((CHANNEL) == DFSDM1_Channel1) || \ 659 ((CHANNEL) == DFSDM1_Channel2) || \ 660 ((CHANNEL) == DFSDM1_Channel3) || \ 661 ((CHANNEL) == DFSDM2_Channel0) || \ 662 ((CHANNEL) == DFSDM2_Channel1) || \ 663 ((CHANNEL) == DFSDM2_Channel2) || \ 664 ((CHANNEL) == DFSDM2_Channel3) || \ 665 ((CHANNEL) == DFSDM2_Channel4) || \ 666 ((CHANNEL) == DFSDM2_Channel5) || \ 667 ((CHANNEL) == DFSDM2_Channel6) || \ 668 ((CHANNEL) == DFSDM2_Channel7)) 669 670 #define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \ 671 ((FILTER) == DFSDM1_1) || \ 672 ((FILTER) == DFSDM2_0) || \ 673 ((FILTER) == DFSDM2_1) || \ 674 ((FILTER) == DFSDM2_2) || \ 675 ((FILTER) == DFSDM2_3)) 676 677 #define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \ 678 ((FILTER) == DFSDM1_1) || \ 679 ((FILTER) == DFSDM2_0) || \ 680 ((FILTER) == DFSDM2_1) || \ 681 ((FILTER) == DFSDM2_2) || \ 682 ((FILTER) == DFSDM2_3)) 683 #else 684 #define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \ 685 ((CHANNEL) == DFSDM1_Channel1) || \ 686 ((CHANNEL) == DFSDM1_Channel2) || \ 687 ((CHANNEL) == DFSDM1_Channel3)) 688 689 #define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \ 690 ((FILTER) == DFSDM1_1)) 691 692 #define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \ 693 ((FILTER) == DFSDM1_1)) 694 #endif /* STM32F413_423xx */ 695 696 697 698 699 #define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO) (((RATIO) < 0x401) && ((RATIO) >= 0x001)) 700 701 #define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO) (((RATIO) < 0x101 ) && ((RATIO) >= 0x001)) 702 703 #define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ((DIVIDER) < 0x101 ) 704 705 #define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ((VALUE) < 256) 706 707 #define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO) ((RATIO) < 33) && ((RATIO) >= 0x001) 708 709 #define IS_DFSDM_HIGH_THRESHOLD(VALUE) ((VALUE) < 0x1000000) 710 #define IS_DFSDM_LOW_THRESHOLD(VALUE) ((VALUE) < 0x1000000) 711 /** 712 * @} 713 */ 714 715 /* Exported macro ------------------------------------------------------------*/ 716 /* Exported functions ------------------------------------------------------- */ 717 718 /* Initialization functions ***************************************************/ 719 void DFSDM_DeInit(void); 720 void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct); 721 void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct); 722 void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct); 723 void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct); 724 725 /* Configuration functions ****************************************************/ 726 #if defined(STM32F412xG) 727 void DFSDM_Command(FunctionalState NewState); 728 #else /* STM32F413_423xx */ 729 void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState); 730 #endif /* STM32F412xG */ 731 void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState); 732 void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState); 733 #if defined(STM32F412xG) 734 void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision); 735 void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource); 736 #else 737 void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision); 738 void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource); 739 #endif /* STM32F412xG */ 740 void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode); 741 void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx); 742 void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx); 743 void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx); 744 void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx); 745 void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx); 746 void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx); 747 void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState); 748 void DFSDM_InjectedContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState); 749 void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState); 750 void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge); 751 void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState); 752 void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState); 753 void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold); 754 void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode); 755 void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio); 756 uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx); 757 void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold); 758 void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx); 759 int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx); 760 int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx); 761 int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx); 762 int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx); 763 int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx); 764 int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx); 765 uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx); 766 void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState); 767 /* Interrupts and flags management functions **********************************/ 768 void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState); 769 #if defined(STM32F412xG) 770 void DFSDM_ITClockAbsenceCmd(FunctionalState NewState); 771 void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState); 772 #else /* STM32F413_423xx */ 773 void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState); 774 void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState); 775 #endif /* STM32F412xG */ 776 777 FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG); 778 #if defined(STM32F412xG) 779 FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence); 780 FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD); 781 #else /* STM32F413_423xx */ 782 FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence); 783 FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD); 784 #endif /* STM32F412xG */ 785 FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold); 786 787 void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF); 788 #if defined(STM32F412xG) 789 void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence); 790 void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD); 791 #else /* STM32F413_423xx */ 792 void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence); 793 void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD); 794 #endif /* STM32F412xG */ 795 void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold); 796 797 ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT); 798 #if defined(STM32F412xG) 799 ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence); 800 ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR); 801 #else /* STM32F413_423xx */ 802 ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence); 803 ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR); 804 #endif /* STM32F412xG */ 805 806 #endif /* STM32F412xG || STM32F413_423xx */ 807 808 #ifdef __cplusplus 809 } 810 #endif 811 812 #endif /*__STM32F4XX_DFSDM_H */ 813 814 /** 815 * @} 816 */ 817 818 /** 819 * @} 820 */ 821 822