1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_EGU_H__
33 #define NRF_EGU_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_egu_hal EGU HAL
43 * @{
44 * @ingroup nrf_egu
45 * @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
46 */
47
48 /** @brief EGU tasks. */
49 typedef enum
50 {
51 NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
52 NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
53 NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
54 NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
55 NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
56 NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
57 NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
58 NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
59 NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
60 NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
61 NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
62 NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
63 NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
64 NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
65 NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
66 NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
67 } nrf_egu_task_t;
68
69 /** @brief EGU events. */
70 typedef enum
71 {
72 NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
73 NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
74 NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
75 NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
76 NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
77 NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
78 NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
79 NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
80 NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
81 NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
82 NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
83 NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
84 NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
85 NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
86 NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
87 NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
88 } nrf_egu_event_t;
89
90 /** @brief EGU interrupts. */
91 typedef enum
92 {
93 NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
94 NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */
95 NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */
96 NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */
97 NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */
98 NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */
99 NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */
100 NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */
101 NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */
102 NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */
103 NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
104 NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
105 NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
106 NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
107 NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
108 NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
109 NRF_EGU_INT_ALL = 0xFFFFuL
110 } nrf_egu_int_mask_t;
111
112
113 /**
114 * @brief Function for getting the maximum channel number of the given EGU.
115 *
116 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
117 *
118 * @return Number of available channels.
119 */
120 NRF_STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type const * p_reg);
121
122 /**
123 * @brief Function for triggering the specified EGU task.
124 *
125 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
126 * @param[in] egu_task EGU task.
127 */
128 NRF_STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * p_reg, nrf_egu_task_t egu_task);
129
130 /**
131 * @brief Function for returning the address of the specified EGU task register.
132 *
133 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
134 * @param[in] egu_task EGU task.
135 *
136 * @return Address of the specified EGU task register.
137 */
138 NRF_STATIC_INLINE uint32_t nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,
139 nrf_egu_task_t egu_task);
140
141 /**
142 * @brief Function for returning the specified EGU TRIGGER task.
143 *
144 * @param[in] channel Channel number.
145 *
146 * @return The specified EGU TRIGGER task.
147 */
148 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel);
149
150 /**
151 * @brief Function for retrieving the state of the UARTE event.
152 *
153 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
154 * @param[in] egu_event EGU event to be checked.
155 *
156 * @retval true The event has been generated.
157 * @retval false The event has not been generated.
158 */
159 NRF_STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type const * p_reg, nrf_egu_event_t egu_event);
160
161 /**
162 * @brief Function for clearing the specified EGU event.
163 *
164 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
165 * @param[in] egu_event EGU event to clear.
166 */
167 NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t egu_event);
168
169 /**
170 * @brief Function for returning the address of the specified EGU event register.
171 *
172 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
173 * @param[in] egu_event EGU event.
174 *
175 * @return Address of the specified EGU event register.
176 */
177 NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,
178 nrf_egu_event_t egu_event);
179
180 /**
181 * @brief Function for returning the specified EGU TRIGGERED event.
182 *
183 * @param[in] channel Channel number.
184 *
185 * @return The specified EGU TRIGGERED event.
186 */
187 NRF_STATIC_INLINE nrf_egu_event_t nrf_egu_triggered_event_get(uint8_t channel);
188
189 /**
190 * @brief Function for enabling one or more of the EGU interrupts.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] mask Mask of interrupts to be enabled.
194 */
195 NRF_STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask);
196
197 /**
198 * @brief Function for retrieving the state of one or more of the EGU interrupts.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] mask Mask of interrupts to be checked.
202 *
203 * @return Mask of enabled interrupts.
204 */
205 NRF_STATIC_INLINE uint32_t nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg, uint32_t mask);
206
207 /**
208 * @brief Function for disabling one or more of the EGU interrupts.
209 *
210 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
211 * @param[in] mask Mask of interrupts to be disabled.
212 */
213 NRF_STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask);
214
215 /**
216 * @brief Function for retrieving the state of interrupt of the specified EGU channel.
217 *
218 * @param[in] channel Channel number.
219 *
220 * @return EGU interrupt mask.
221 */
222 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel);
223
224 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
225 /**
226 * @brief Function for setting the subscribe configuration for a given
227 * EGU task.
228 *
229 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
230 * @param[in] task Task for which to set the configuration.
231 * @param[in] channel Channel through which to subscribe events.
232 */
233 NRF_STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
234 nrf_egu_task_t task,
235 uint8_t channel);
236
237 /**
238 * @brief Function for clearing the subscribe configuration for a given
239 * EGU task.
240 *
241 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242 * @param[in] task Task for which to clear the configuration.
243 */
244 NRF_STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
245 nrf_egu_task_t task);
246
247 /**
248 * @brief Function for setting the publish configuration for a given
249 * EGU event.
250 *
251 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
252 * @param[in] event Event for which to set the configuration.
253 * @param[in] channel Channel through which to publish the event.
254 */
255 NRF_STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
256 nrf_egu_event_t event,
257 uint8_t channel);
258
259 /**
260 * @brief Function for clearing the publish configuration for a given
261 * EGU event.
262 *
263 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
264 * @param[in] event Event for which to clear the configuration.
265 */
266 NRF_STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
267 nrf_egu_event_t event);
268 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
269
270 #ifndef NRF_DECLARE_ONLY
271
nrf_egu_channel_count(NRF_EGU_Type const * p_reg)272 NRF_STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type const * p_reg)
273 {
274 if (p_reg == NRF_EGU0){
275 return EGU0_CH_NUM;
276 }
277 #if EGU_COUNT > 1
278 if (p_reg == NRF_EGU1){
279 return EGU1_CH_NUM;
280 }
281 #endif
282 #if EGU_COUNT > 2
283 if (p_reg == NRF_EGU2){
284 return EGU2_CH_NUM;
285 }
286 if (p_reg == NRF_EGU3){
287 return EGU3_CH_NUM;
288 }
289 if (p_reg == NRF_EGU4){
290 return EGU4_CH_NUM;
291 }
292 if (p_reg == NRF_EGU5){
293 return EGU5_CH_NUM;
294 }
295 #endif
296 return 0;
297 }
298
nrf_egu_task_trigger(NRF_EGU_Type * p_reg,nrf_egu_task_t egu_task)299 NRF_STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * p_reg, nrf_egu_task_t egu_task)
300 {
301 NRFX_ASSERT(p_reg);
302 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_task)) = 0x1UL;
303 }
304
nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,nrf_egu_task_t egu_task)305 NRF_STATIC_INLINE uint32_t nrf_egu_task_address_get(NRF_EGU_Type const * p_reg,
306 nrf_egu_task_t egu_task)
307 {
308 NRFX_ASSERT(p_reg);
309 return (uint32_t)((uint8_t *)p_reg + (uint32_t)egu_task);
310 }
311
nrf_egu_trigger_task_get(uint8_t channel)312 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel)
313 {
314 return (nrf_egu_task_t)NRFX_OFFSETOF(NRF_EGU_Type, TASKS_TRIGGER[channel]);
315 }
316
nrf_egu_event_check(NRF_EGU_Type const * p_reg,nrf_egu_event_t egu_event)317 NRF_STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type const * p_reg, nrf_egu_event_t egu_event)
318 {
319 NRFX_ASSERT(p_reg);
320 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event);
321 }
322
nrf_egu_event_clear(NRF_EGU_Type * p_reg,nrf_egu_event_t egu_event)323 NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t egu_event)
324 {
325 NRFX_ASSERT(p_reg);
326 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event)) = 0x0UL;
327 nrf_event_readback((uint8_t *)p_reg + (uint32_t)egu_event);
328 }
329
nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,nrf_egu_event_t egu_event)330 NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,
331 nrf_egu_event_t egu_event)
332 {
333 NRFX_ASSERT(p_reg);
334 return (uint32_t)((uint8_t *)p_reg + (uint32_t)egu_event);
335 }
336
nrf_egu_triggered_event_get(uint8_t channel)337 NRF_STATIC_INLINE nrf_egu_event_t nrf_egu_triggered_event_get(uint8_t channel)
338 {
339 return (nrf_egu_event_t)NRFX_OFFSETOF(NRF_EGU_Type, EVENTS_TRIGGERED[channel]);
340 }
341
nrf_egu_int_enable(NRF_EGU_Type * p_reg,uint32_t mask)342 NRF_STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask)
343 {
344 NRFX_ASSERT(p_reg);
345 p_reg->INTENSET = mask;
346 }
347
nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg,uint32_t mask)348 NRF_STATIC_INLINE uint32_t nrf_egu_int_enable_check(NRF_EGU_Type const * p_reg, uint32_t mask)
349 {
350 NRFX_ASSERT(p_reg);
351 return p_reg->INTENSET & mask;
352 }
353
nrf_egu_int_disable(NRF_EGU_Type * p_reg,uint32_t mask)354 NRF_STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask)
355 {
356 NRFX_ASSERT(p_reg);
357 p_reg->INTENCLR = mask;
358 }
359
nrf_egu_channel_int_get(uint8_t channel)360 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel)
361 {
362 return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
363 }
364
365 #if defined(DPPI_PRESENT)
nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,nrf_egu_task_t task,uint8_t channel)366 NRF_STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
367 nrf_egu_task_t task,
368 uint8_t channel)
369 {
370 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
371 ((uint32_t)channel | EGU_SUBSCRIBE_TRIGGER_EN_Msk);
372 }
373
nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,nrf_egu_task_t task)374 NRF_STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
375 nrf_egu_task_t task)
376 {
377 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
378 }
379
nrf_egu_publish_set(NRF_EGU_Type * p_reg,nrf_egu_event_t event,uint8_t channel)380 NRF_STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
381 nrf_egu_event_t event,
382 uint8_t channel)
383 {
384 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
385 ((uint32_t)channel | EGU_PUBLISH_TRIGGERED_EN_Msk);
386 }
387
nrf_egu_publish_clear(NRF_EGU_Type * p_reg,nrf_egu_event_t event)388 NRF_STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
389 nrf_egu_event_t event)
390 {
391 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
392 }
393 #endif // defined(DPPI_PRESENT)
394
395 #endif // NRF_DECLARE_ONLY
396
397 /** @} */
398
399 #ifdef __cplusplus
400 }
401 #endif
402
403 #endif
404