1 /* 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _HARDWARE_PLL_H 8 #define _HARDWARE_PLL_H 9 10 #include "pico.h" 11 #include "hardware/structs/pll.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /** \file hardware/pll.h 18 * \defgroup hardware_pll hardware_pll 19 * 20 * Phase Locked Loop control APIs 21 * 22 * There are two PLLs in RP2040. They are: 23 * - pll_sys - Used to generate up to a 133MHz system clock 24 * - pll_usb - Used to generate a 48MHz USB reference clock 25 * 26 * For details on how the PLLs are calculated, please refer to the RP2040 datasheet. 27 */ 28 29 typedef pll_hw_t *PLL; 30 31 #define pll_sys pll_sys_hw 32 #define pll_usb pll_usb_hw 33 34 #ifndef PICO_PLL_VCO_MIN_FREQ_KHZ 35 #ifndef PICO_PLL_VCO_MIN_FREQ_MHZ 36 #define PICO_PLL_VCO_MIN_FREQ_KHZ (750 * KHZ) 37 #else 38 #define PICO_PLL_VCO_MIN_FREQ_KHZ (PICO_PLL_VCO_MIN_FREQ_MHZ * KHZ) 39 #endif 40 #endif 41 42 #ifndef PICO_PLL_VCO_MAX_FREQ_KHZ 43 #ifndef PICO_PLL_VCO_MAX_FREQ_MHZ 44 #define PICO_PLL_VCO_MAX_FREQ_KHZ (1600 * KHZ) 45 #else 46 #define PICO_PLL_VCO_MAX_FREQ_KHZ (PICO_PLL_VCO_MAX_FREQ_MHZ * KHZ) 47 #endif 48 #endif 49 50 /*! \brief Initialise specified PLL. 51 * \ingroup hardware_pll 52 * \param pll pll_sys or pll_usb 53 * \param ref_div Input clock divider. 54 * \param vco_freq Requested output from the VCO (voltage controlled oscillator) 55 * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2 56 * \param post_div2 Post Divider 2 - range 1-7 57 */ 58 void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2); 59 60 /*! \brief Release/uninitialise specified PLL. 61 * \ingroup hardware_pll 62 * 63 * This will turn off the power to the specified PLL. Note this function does not currently check if 64 * the PLL is in use before powering it off so should be used with care. 65 * 66 * \param pll pll_sys or pll_usb 67 */ 68 void pll_deinit(PLL pll); 69 70 71 #ifdef __cplusplus 72 } 73 #endif 74 75 #endif 76