1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_TIMER_H 10 #define _HARDWARE_STRUCTS_TIMER_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/timer.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/timer.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct { 24 _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW 25 // Write to bits 63:32 of time 26 io_wo_32 timehw; 27 28 _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW 29 // Write to bits 31:0 of time 30 io_wo_32 timelw; 31 32 _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR 33 // Read from bits 63:32 of time 34 io_ro_32 timehr; 35 36 _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR 37 // Read from bits 31:0 of time 38 io_ro_32 timelr; 39 40 _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 41 // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) 42 // 43 // Arm alarm 0, and configure the time it will fire 44 io_rw_32 alarm[NUM_TIMERS]; // 4 45 46 _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED 47 // Indicates the armed/disarmed status of each alarm 48 // 0x0000000f [3:0] : ARMED (0) 49 io_rw_32 armed; 50 51 _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH 52 // Raw read from bits 63:32 of time (no side effects) 53 io_ro_32 timerawh; 54 55 _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL 56 // Raw read from bits 31:0 of time (no side effects) 57 io_ro_32 timerawl; 58 59 _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE 60 // Set bits high to enable pause when the corresponding debug ports are active 61 // 0x00000004 [2] : DBG1 (1): Pause when processor 1 is in debug mode 62 // 0x00000002 [1] : DBG0 (1): Pause when processor 0 is in debug mode 63 io_rw_32 dbgpause; 64 65 _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE 66 // Set high to pause the timer 67 // 0x00000001 [0] : PAUSE (0) 68 io_rw_32 pause; 69 70 _REG_(TIMER_INTR_OFFSET) // TIMER_INTR 71 // Raw Interrupts 72 // 0x00000008 [3] : ALARM_3 (0) 73 // 0x00000004 [2] : ALARM_2 (0) 74 // 0x00000002 [1] : ALARM_1 (0) 75 // 0x00000001 [0] : ALARM_0 (0) 76 io_rw_32 intr; 77 78 _REG_(TIMER_INTE_OFFSET) // TIMER_INTE 79 // Interrupt Enable 80 // 0x00000008 [3] : ALARM_3 (0) 81 // 0x00000004 [2] : ALARM_2 (0) 82 // 0x00000002 [1] : ALARM_1 (0) 83 // 0x00000001 [0] : ALARM_0 (0) 84 io_rw_32 inte; 85 86 _REG_(TIMER_INTF_OFFSET) // TIMER_INTF 87 // Interrupt Force 88 // 0x00000008 [3] : ALARM_3 (0) 89 // 0x00000004 [2] : ALARM_2 (0) 90 // 0x00000002 [1] : ALARM_1 (0) 91 // 0x00000001 [0] : ALARM_0 (0) 92 io_rw_32 intf; 93 94 _REG_(TIMER_INTS_OFFSET) // TIMER_INTS 95 // Interrupt status after masking & forcing 96 // 0x00000008 [3] : ALARM_3 (0) 97 // 0x00000004 [2] : ALARM_2 (0) 98 // 0x00000002 [1] : ALARM_1 (0) 99 // 0x00000001 [0] : ALARM_0 (0) 100 io_ro_32 ints; 101 } timer_hw_t; 102 103 #define timer_hw ((timer_hw_t *)TIMER_BASE) 104 105 static_assert( NUM_TIMERS == 4, ""); 106 107 #endif 108