1 /*
2 * @brief LPC15xx DMA chip driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #include "chip.h"
33
34 /*****************************************************************************
35 * Private types/enumerations/variables
36 ****************************************************************************/
37
38 /*****************************************************************************
39 * Public types/enumerations/variables
40 ****************************************************************************/
41
42 /* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
43 function if a DMA SRAM table is needed. This table is correctly aligned for
44 the DMA controller. */
45 #if defined(__CC_ARM)
46 /* Keil alignement to 512 bytes */
47 __align(512) DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
48 #endif /* defined (__CC_ARM) */
49
50 /* IAR support */
51 #if defined(__ICCARM__)
52 /* IAR EWARM alignement to 512 bytes */
53 #pragma data_alignment=512
54 DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
55 #endif /* defined (__ICCARM__) */
56
57 #if defined( __GNUC__ )
58 /* GNU alignement to 512 bytes */
59 DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL] __attribute__ ((aligned(512)));
60 #endif /* defined (__GNUC__) */
61
62 /*****************************************************************************
63 * Private functions
64 ****************************************************************************/
65
66 /*****************************************************************************
67 * Public functions
68 ****************************************************************************/
69
70 /* Set DMA transfer register interrupt bits (safe) */
Chip_DMA_SetTranBits(LPC_DMA_T * pDMA,DMA_CHID_T ch,uint32_t mask)71 void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
72 {
73 uint32_t temp;
74
75 /* Read and write values may not be the same, write 0 to
76 undefined bits */
77 temp = pDMA->DMACH[ch].XFERCFG & ~0xFC000CC0;
78
79 pDMA->DMACH[ch].XFERCFG = temp | mask;
80 }
81
82 /* Clear DMA transfer register interrupt bits (safe) */
Chip_DMA_ClearTranBits(LPC_DMA_T * pDMA,DMA_CHID_T ch,uint32_t mask)83 void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
84 {
85 uint32_t temp;
86
87 /* Read and write values may not be the same, write 0 to
88 undefined bits */
89 temp = pDMA->DMACH[ch].XFERCFG & ~0xFC000CC0;
90
91 pDMA->DMACH[ch].XFERCFG = temp & ~mask;
92 }
93
94 /* Update the transfer size in an existing DMA channel transfer configuration */
Chip_DMA_SetupChannelTransferSize(LPC_DMA_T * pDMA,DMA_CHID_T ch,uint32_t trans)95 void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans)
96 {
97 Chip_DMA_ClearTranBits(pDMA, ch, (0x3FF << 16));
98 Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_XFERCOUNT(trans));
99 }
100
101 /* Sets up a DMA channel with the passed DMA transfer descriptor */
Chip_DMA_SetupTranChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch,DMA_CHDESC_T * desc)102 bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc)
103 {
104 bool good = false;
105 DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) pDMA->SRAMBASE;
106
107 if ((Chip_DMA_GetActiveChannels(pDMA) & (1 << ch)) == 0) {
108 /* Channel is not active, so update the descriptor */
109 pDesc[ch] = *desc;
110
111 good = true;
112 }
113
114 return good;
115 }
116