1 /*
2 * Copyright (c) 2012-2013 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/debug.h>
9 #include <stdio.h>
10 #include <lk/compiler.h>
11 #include <stdint.h>
12 #include <lk/bits.h>
13 #include <kernel/thread.h>
14 #include <arch/arm/cm.h>
15 #include <platform.h>
16
17 #pragma GCC diagnostic ignored "-Wmissing-declarations"
18
dump_frame(const struct arm_cm_exception_frame * frame)19 static void dump_frame(const struct arm_cm_exception_frame *frame) {
20
21 printf("exception frame at %p\n", frame);
22 printf("\tr0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x r4 0x%08x\n",
23 frame->r0, frame->r1, frame->r2, frame->r3, frame->r4);
24 printf("\tr5 0x%08x r6 0x%08x r7 0x%08x r8 0x%08x r9 0x%08x\n",
25 frame->r5, frame->r6, frame->r7, frame->r8, frame->r9);
26 printf("\tr10 0x%08x r11 0x%08x r12 0x%08x\n",
27 frame->r10, frame->r11, frame->r12);
28 printf("\tlr 0x%08x pc 0x%08x psr 0x%08x\n",
29 frame->lr, frame->pc, frame->psr);
30 }
31
hardfault(struct arm_cm_exception_frame * frame)32 void hardfault(struct arm_cm_exception_frame *frame) {
33 printf("hardfault: ");
34 dump_frame(frame);
35
36 #if (__CORTEX_M >= 0X03) || (__CORTEX_SC >= 300)
37 printf("HFSR 0x%x\n", SCB->HFSR);
38 #endif
39
40 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
41 }
42
memmanage(struct arm_cm_exception_frame * frame)43 void memmanage(struct arm_cm_exception_frame *frame) {
44 printf("memmanage: ");
45 dump_frame(frame);
46
47 #if (__CORTEX_M >= 0X03) || (__CORTEX_SC >= 300)
48 uint32_t mmfsr = SCB->CFSR & 0xff;
49
50 if (mmfsr & (1<<0)) { // IACCVIOL
51 printf("instruction fault\n");
52 }
53 if (mmfsr & (1<<1)) { // DACCVIOL
54 printf("data fault\n");
55 }
56 if (mmfsr & (1<<3)) { // MUNSTKERR
57 printf("fault on exception return\n");
58 }
59 if (mmfsr & (1<<4)) { // MSTKERR
60 printf("fault on exception entry\n");
61 }
62 if (mmfsr & (1<<5)) { // MLSPERR
63 printf("fault on lazy fpu preserve\n");
64 }
65 if (mmfsr & (1<<7)) { // MMARVALID
66 printf("fault address 0x%x\n", SCB->MMFAR);
67 }
68 #endif
69 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
70 }
71
72
usagefault(struct arm_cm_exception_frame * frame)73 void usagefault(struct arm_cm_exception_frame *frame) {
74 printf("usagefault: ");
75 dump_frame(frame);
76
77 #if (__CORTEX_M >= 0x03)
78 uint32_t ufsr = BITS_SHIFT(SCB->CFSR, 31, 16);
79 printf("UFSR 0x%x: ", ufsr);
80
81 if (ufsr & (1<<0))
82 printf("undefined instruction\n");
83 if (ufsr & (1<<1))
84 printf("ESPR invalid\n");
85 if (ufsr & (1<<2))
86 printf("integrity check failed on EXC_RETURN\n");
87 if (ufsr & (1<<3))
88 printf("coprocessor access error\n");
89 if (ufsr & (1<<8))
90 printf("unaligned error\n");
91 if (ufsr & (1<<9))
92 printf("division by zero\n");
93 #endif
94
95 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
96 }
97
busfault(struct arm_cm_exception_frame * frame)98 void busfault(struct arm_cm_exception_frame *frame) {
99 printf("busfault: ");
100 dump_frame(frame);
101
102 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
103 }
104
105 /* raw exception vectors */
106
_nmi(void)107 void _nmi(void) {
108 printf("nmi\n");
109 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
110 }
111
112 /* Declare two versions of the assembly to push the extra registers
113 * not already saved by the exception delivery hardware. For armv6-m
114 * based hardware we cannot directly push the higher registers so we
115 * need to move them into lower registers before pushing.
116 */
117 #if (__CORTEX_M >= 0X03) || (__CORTEX_SC >= 300)
118 #define PUSH_REGS \
119 "push {r4-r11, lr};" /* 9 words on the stack */
120 #else
121 #define PUSH_REGS \
122 "push {r4-r7, lr};" /* 5 words */ \
123 "mov r4, r8;" \
124 "mov r5, r9;" \
125 "mov r6, r10;" \
126 "mov r7, r11;" \
127 "push {r4-r7};" /* 4 more words */
128 #endif
129
_hardfault(void)130 __NAKED void _hardfault(void) {
131 __asm__ volatile(
132 PUSH_REGS
133 "mov r0, sp;"
134 "sub sp, #4;" /* adjust the stack to be 8 byte aligned */
135 "b hardfault;"
136 );
137 }
138
_memmanage(void)139 __NAKED void _memmanage(void) {
140 __asm__ volatile(
141 PUSH_REGS
142 "mov r0, sp;"
143 "sub sp, #4;" /* adjust the stack to be 8 byte aligned */
144 "b memmanage;"
145 );
146 }
147
_busfault(void)148 __NAKED void _busfault(void) {
149 __asm__ volatile(
150 PUSH_REGS
151 "mov r0, sp;"
152 "sub sp, #4;" /* adjust the stack to be 8 byte aligned */
153 "b busfault;"
154 );
155 }
156
_usagefault(void)157 __NAKED void _usagefault(void) {
158 __asm__ volatile(
159 PUSH_REGS
160 "mov r0, sp;"
161 "sub sp, #4;" /* adjust the stack to be 8 byte aligned */
162 "b usagefault;"
163 );
164 }
165
166 #undef PUSH_REGS
167
168 /* declared weak so these can be overridden elsewhere */
169
170 /* systick handler */
_systick(void)171 void __WEAK _systick(void) {
172 printf("systick\n");
173 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
174 }
175
_debugmonitor(void)176 void __WEAK _debugmonitor(void) {
177 printf("debugmonitor\n");
178 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
179 }
180
_svc(void)181 void __WEAK _svc(void) {
182 printf("svc\n");
183 platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
184 }
185