Searched refs:RISCV_CSR_XSTATUS (Results 1 – 8 of 8) sorted by relevance
| /arch/riscv/include/arch/ |
| A D | arch_ops.h | 17 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE); in arch_enable_ints()
21 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE); in arch_disable_ints()
25 return !(riscv_csr_read(RISCV_CSR_XSTATUS) & RISCV_CSR_XSTATUS_IE); in arch_ints_disabled()
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| A D | spinlock.h | 53 *statep = riscv_csr_read_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE) & RISCV_CSR_XSTATUS_IE; in arch_interrupt_save()
59 riscv_csr_set(RISCV_CSR_XSTATUS, old_state); in arch_interrupt_restore()
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| A D | riscv.h | 43 #define RISCV_CSR_XSTATUS __CONCAT(RISCV_MODE_PREFIX, status) macro
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| /arch/riscv/ |
| A D | thread.c | 68 ulong status = riscv_csr_read(RISCV_CSR_XSTATUS); in arch_context_switch()
100 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in arch_context_switch()
101 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_CLEAN); in arch_context_switch()
111 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in arch_context_switch()
112 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_INITIAL); in arch_context_switch()
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| A D | arch.c | 56 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE); in riscv_early_init_percpu()
61 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in riscv_early_init_percpu()
62 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_INITIAL); in riscv_early_init_percpu()
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| A D | fpu_asm.S | 75 csrs RISCV_CSR_XSTATUS, a0
77 csrc RISCV_CSR_XSTATUS, a0
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| A D | asm.S | 87 csrr t0, RISCV_CSR_XSTATUS
104 csrw RISCV_CSR_XSTATUS, t0
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| A D | mmu.cpp | 607 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_SUM); in riscv_mmu_init_secondaries()
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