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Searched refs:RISCV_CSR_XSTATUS_FS_MASK (Results 1 – 3 of 3) sorted by relevance

/arch/riscv/
A Dthread.c69 ulong hw_state = status & RISCV_CSR_XSTATUS_FS_MASK; in arch_context_switch()
100 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in arch_context_switch()
111 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in arch_context_switch()
A Darch.c61 riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_FS_MASK); in riscv_early_init_percpu()
/arch/riscv/include/arch/
A Driscv.h83 #define RISCV_CSR_XSTATUS_FS_MASK (3ul << RISCV_CSR_XSTATUS_FS_SHIFT) macro

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