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Searched refs:RISCV_INTERRUPT_MSWI (Results 1 – 2 of 2) sorted by relevance

/arch/riscv/
A Dexceptions.c57 case RISCV_INTERRUPT_MSWI: in cause_to_string()
/arch/riscv/include/arch/
A Driscv.h107 #define RISCV_INTERRUPT_MSWI 3 macro

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