Home
last modified time | relevance | path

Searched refs:RISCV_INTERRUPT_SSWI (Results 1 – 2 of 2) sorted by relevance

/arch/riscv/
A Dexceptions.c55 case RISCV_INTERRUPT_SSWI: in cause_to_string()
/arch/riscv/include/arch/
A Driscv.h106 #define RISCV_INTERRUPT_SSWI 1 macro

Completed in 5 milliseconds