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Searched refs:RISCV_INTERRUPT_XSWI (Results 1 – 2 of 2) sorted by relevance

/arch/riscv/
A Dexceptions.c120 case RISCV_INTERRUPT_XSWI: // machine software interrupt in riscv_exception_handler()
/arch/riscv/include/arch/
A Driscv.h116 #define RISCV_INTERRUPT_XSWI (RISCV_XMODE_OFFSET) macro

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