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Searched refs:addr (Results 1 – 6 of 6) sorted by relevance

/arch/arm64/include/arch/
A Dreg.h20 #define _ARCH_MMIO_READ8(addr) ({ \ argument
25 #define _ARCH_MMIO_READ16(addr) ({ \ argument
30 #define _ARCH_MMIO_READ32(addr) ({ \ argument
35 #define _ARCH_MMIO_READ64(addr) ({ \ argument
41 #define _ARCH_MMIO_WRITE8(addr, val) \ argument
43 #define _ARCH_MMIO_WRITE16(addr, val) \ argument
44 __asm__ volatile("strh %w1, %0" : "=m"(*(addr)): "r"(val) : "memory")
45 #define _ARCH_MMIO_WRITE32(addr, val) \ argument
46 __asm__ volatile("str %w1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
47 #define _ARCH_MMIO_WRITE64(addr, val) \ argument
[all …]
/arch/x86/include/arch/
A Dreg.h23 #define _ARCH_MMIO_READ8(addr) ({ \ argument
25 __asm__ volatile("movb %1, %0" : "=q"(val) : "m"(*(addr)) : "memory"); \
28 #define _ARCH_MMIO_READ16(addr) ({ \ argument
33 #define _ARCH_MMIO_READ32(addr) ({ \ argument
39 #define _ARCH_MMIO_READ64(addr) ({ \ argument
46 #define _ARCH_MMIO_WRITE8(addr, val) \ argument
47 __asm__ volatile("movb %1, %0" : "=m"(*(addr)) : "iq"(val) : "memory")
48 #define _ARCH_MMIO_WRITE16(addr, val) \ argument
49 __asm__ volatile("movw %1, %0" : "=m"(*(addr)) : "ir"(val) : "memory")
50 #define _ARCH_MMIO_WRITE32(addr, val) \ argument
[all …]
/arch/arm/include/arch/
A Dreg.h20 #define _ARCH_MMIO_READ8(addr) ({ \ argument
22 __asm__ volatile("ldrb %0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
25 #define _ARCH_MMIO_READ16(addr) ({ \ argument
30 #define _ARCH_MMIO_READ32(addr) ({ \ argument
32 __asm__ volatile("ldr %0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
36 #define _ARCH_MMIO_WRITE8(addr, val) \ argument
37 __asm__ volatile("strb %1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
38 #define _ARCH_MMIO_WRITE16(addr, val) \ argument
39 __asm__ volatile("strh %1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
40 #define _ARCH_MMIO_WRITE32(addr, val) \ argument
[all …]
/arch/or1k/
A Dcache-ops.c76 addr_t addr; in arch_clean_cache_range() local
79 for (addr = start; addr < start + len; addr += block_size) in arch_clean_cache_range()
80 mtspr(OR1K_SPR_DCACHE_DCBFR_ADDR, addr); in arch_clean_cache_range()
85 addr_t addr; in arch_invalidate_cache_range() local
88 for (addr = start; addr < start + len; addr += block_size) in arch_invalidate_cache_range()
89 mtspr(OR1K_SPR_DCACHE_DCBIR_ADDR, addr); in arch_invalidate_cache_range()
100 addr_t addr; in arch_sync_cache_range() local
104 for (addr = start; addr < start + len; addr += block_size) in arch_sync_cache_range()
105 mtspr(OR1K_SPR_ICACHE_ICBIR_ADDR, addr); in arch_sync_cache_range()
A Dfaults.c48 void or1k_busfault_handler(struct or1k_iframe *frame, uint32_t addr) { in or1k_busfault_handler() argument
49 dprintf(CRITICAL, "unhandled busfault (EEAR: 0x%08x)", addr); in or1k_busfault_handler()
53 void or1k_data_pagefault_handler(struct or1k_iframe *frame, uint32_t addr) { in or1k_data_pagefault_handler() argument
54 dprintf(CRITICAL, "unhandled data pagefault (EEAR: 0x%08x)", addr); in or1k_data_pagefault_handler()
58 void or1k_instruction_pagefault_handler(struct or1k_iframe *frame, uint32_t addr) { in or1k_instruction_pagefault_handler() argument
59 dprintf(CRITICAL, "unhandled instruction pagefault (EEAR: 0x%08x)", addr); in or1k_instruction_pagefault_handler()
63 void or1k_alignment_handler(struct or1k_iframe *frame, uint32_t addr) { in or1k_alignment_handler() argument
64 dprintf(CRITICAL, "unhandled unaligned access (EEAR: 0x%08x)", addr); in or1k_alignment_handler()
68 void or1k_illegal_instruction_handler(struct or1k_iframe *frame, uint32_t addr) { in or1k_illegal_instruction_handler() argument
69 dprintf(CRITICAL, "unhandled illegal instruction (EEAR: 0x%08x)", addr); in or1k_illegal_instruction_handler()
/arch/x86/64/
A Dmmu.c59 uint64_t addr = (uint64_t)vaddr; in x86_mmu_check_vaddr() local
64 if (!IS_ALIGNED(addr, PAGE_SIZE)) in x86_mmu_check_vaddr()
76 if ((addr > max_vaddr_lohalf) && (addr < min_vaddr_hihalf)) in x86_mmu_check_vaddr()

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