Searched refs:reg (Results 1 – 8 of 8) sorted by relevance
| /arch/arm/include/arch/ |
| A D | asm.h | 13 #define LOADCONST(reg, c) \ argument
14 movw reg, #:lower16: c; \
15 movt reg, #:upper16: c
17 #define LOADCONST(reg, c) ldr reg, =##c argument
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| A D | arm.h | 104 #define GEN_CP_REG_FUNCS(cp, reg, op1, c1, c2, op2) \ argument
105 static inline __ALWAYS_INLINE uint32_t arm_read_##reg(void) { \
111 static inline __ALWAYS_INLINE uint32_t arm_read_##reg##_relaxed(void) { \
117 static inline __ALWAYS_INLINE void arm_write_##reg(uint32_t val) { \
122 static inline __ALWAYS_INLINE void arm_write_##reg##_relaxed(uint32_t val) { \
126 #define GEN_CP15_REG_FUNCS(reg, op1, c1, c2, op2) \ argument
127 GEN_CP_REG_FUNCS(p15, reg, op1, c1, c2, op2)
129 #define GEN_CP14_REG_FUNCS(reg, op1, c1, c2, op2) \ argument
130 GEN_CP_REG_FUNCS(p14, reg, op1, c1, c2, op2)
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| /arch/arm64/include/arch/ |
| A D | asm_macros.h | 19 .macro tbzmask, reg, mask, label, shift=0
23 tbz \reg, #\shift, \label
25 tbzmask \reg, \mask, \label, "(\shift + 1)"
29 .macro tbnzmask, reg, mask, label, shift=0
33 tbnz \reg, #\shift, \label
35 tbnzmask \reg, \mask, \label, "(\shift + 1)"
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| A D | arm64.h | 22 #define ARM64_READ_SYSREG(reg) \ argument
25 __asm__ volatile("mrs %0," TOSTRING(reg) : "=r" (_val)); \
29 #define ARM64_WRITE_SYSREG(reg, val) \ argument
31 __asm__ volatile("msr " TOSTRING(reg) ", %0" :: "r" (val)); \
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| /arch/x86/ |
| A D | lapic.c | 99 static uint32_t lapic_read(enum lapic_regs reg) { in lapic_read() argument
100 LTRACEF_LEVEL(2, "reg %#x\n", reg); in lapic_read()
103 DEBUG_ASSERT(reg != LAPIC_ICRLO && reg != LAPIC_ICRHI); in lapic_read()
104 return read_msr(X86_MSR_IA32_X2APIC_BASE + reg / 0x10); in lapic_read()
106 return mmio_read32(lapic_mmio + reg / 4); in lapic_read()
110 static void lapic_write(enum lapic_regs reg, uint32_t val) { in lapic_write() argument
111 LTRACEF_LEVEL(2, "reg %#x val %#x\n", reg, val); in lapic_write()
113 DEBUG_ASSERT(reg != LAPIC_ICRLO && reg != LAPIC_ICRHI); in lapic_write()
114 write_msr(X86_MSR_IA32_X2APIC_BASE + reg / 0x10, val); in lapic_write()
116 mmio_write32(lapic_mmio + reg / 4, val); in lapic_write()
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| A D | feature.c | 117 uint32_t reg[3]; in x86_cpu_detect() member
120 vs.reg[0] = b; in x86_cpu_detect()
121 vs.reg[1] = d; in x86_cpu_detect()
122 vs.reg[2] = c; in x86_cpu_detect()
251 uint32_t reg[3]; in x86_feature_init() member
254 vs.reg[0] = b; in x86_feature_init()
255 vs.reg[1] = d; in x86_feature_init()
256 vs.reg[2] = c; in x86_feature_init()
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| /arch/arm/ |
| A D | stackusage | 76 reg = t[iindex+1] variable
77 if reg == "sp,":
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| /arch/riscv/ |
| A D | fpu_asm.S | 24 .macro ZERO_FPU_REG reg, width
26 fcvt.\width\().w \reg, zero
28 fmv.\width\().x \reg, zero
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