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Searched refs:riscv_csr_write (Results 1 – 4 of 4) sorted by relevance

/arch/riscv/
A Dtime.c46 riscv_csr_write(RISCV_CSR_STIMECMP, ticks); in platform_set_oneshot_timer()
48 riscv_csr_write(RISCV_CSR_STIMECMPH, ticks >> 32); in platform_set_oneshot_timer()
49 riscv_csr_write(RISCV_CSR_STIMECMP, ticks); in platform_set_oneshot_timer()
A Darch.c50 riscv_csr_write(RISCV_CSR_XSCRATCH, 0); in riscv_early_init_percpu()
53 riscv_csr_write(RISCV_CSR_XTVEC, (uintptr_t)&riscv_exception_entry); in riscv_early_init_percpu()
165 riscv_csr_write(sstatus, status); in arch_enter_uspace()
166 riscv_csr_write(sepc, entry_point); in arch_enter_uspace()
167 riscv_csr_write(sscratch, kernel_stack_top); in arch_enter_uspace()
A Dmmu.cpp121 riscv_csr_write(RISCV_CSR_SATP, satp); in riscv_set_satp()
617 riscv_csr_write(satp, satp); in riscv_early_mmu_init()
619 riscv_csr_write(satp, satp_orig); in riscv_early_mmu_init()
/arch/riscv/include/arch/
A Driscv.h182 #define riscv_csr_write(csr, val) \ macro

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