Searched refs:write_msr (Results 1 – 5 of 5) sorted by relevance
| /arch/x86/ |
| A D | lapic.c | 114 write_msr(X86_MSR_IA32_X2APIC_BASE + reg / 0x10, val); in lapic_write()
136 write_msr(X86_MSR_IA32_X2APIC_BASE + 0x30, ((uint64_t)apic_id << 32) | low); in lapic_write_icr()
157 write_msr(X86_MSR_IA32_TSC_DEADLINE, deadline); in lapic_set_oneshot_timer()
177 write_msr(X86_MSR_IA32_TSC_DEADLINE, 0); in lapic_cancel_timer()
231 write_msr(X86_MSR_IA32_APIC_BASE, apic_base); in lapic_init_postvm()
241 write_msr(X86_MSR_IA32_APIC_BASE, apic_base | (1u<<10)); in lapic_init_postvm()
276 write_msr(X86_MSR_IA32_APIC_BASE, apic_base); in lapic_init_percpu()
305 write_msr(X86_MSR_IA32_TSC_DEADLINE, 0); in lapic_timer_init_percpu()
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| A D | mp.c | 51 write_msr(X86_MSR_IA32_KERNEL_GS_BASE, 0); in x86_configure_percpu_early()
52 write_msr(X86_MSR_IA32_GS_BASE, (uint64_t)percpu); in x86_configure_percpu_early()
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| A D | pv.c | 74 write_msr(clocksource_msr_base, paddr); in pvclock_init()
75 write_msr(clocksource_msr_base + 1, paddr + sizeof(struct pvclock_wall_clock) + 1); in pvclock_init()
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| /arch/x86/include/arch/ |
| A D | x86.h | 483 static inline void write_msr (uint32_t msr_id, uint64_t msr_write_val) { in write_msr() function
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| /arch/x86/64/ |
| A D | mmu.c | 655 write_msr(X86_MSR_IA32_EFER, efer_msr); in x86_mmu_early_init_percpu()
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