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Searched refs:reg (Results 1 – 19 of 19) sorted by relevance

/dev/bus/pci/backend/
A Decam.cpp88 inline size_t location_to_offset(const pci_location_t state, uint32_t reg) { in location_to_offset() argument
97 offset += reg; in location_to_offset()
104 auto off = location_to_offset(state, reg); in read_config()
113 auto off = location_to_offset(state, reg); in write_config()
120 int pci_ecam::read_config_byte(const pci_location_t state, uint32_t reg, uint8_t *value) { in read_config_byte() argument
122 return read_config(state, reg, value, ecam_ptr_); in read_config_byte()
127 return read_config(state, reg, value, ecam_ptr_); in read_config_half()
132 return read_config(state, reg, value, ecam_ptr_); in read_config_word()
137 return write_config(state, reg, value, ecam_ptr_); in write_config_byte()
142 return write_config(state, reg, value, ecam_ptr_); in write_config_half()
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A Dpci_backend.h30 virtual int read_config_byte(pci_location_t state, uint32_t reg, uint8_t *value) { in read_config_byte() argument
33 virtual int read_config_half(pci_location_t state, uint32_t reg, uint16_t *value) { in read_config_half() argument
36 virtual int read_config_word(pci_location_t state, uint32_t reg, uint32_t *value) { in read_config_word() argument
40 virtual int write_config_byte(pci_location_t state, uint32_t reg, uint8_t value) { in write_config_byte() argument
43 virtual int write_config_half(pci_location_t state, uint32_t reg, uint16_t value) { in write_config_half() argument
46 virtual int write_config_word(pci_location_t state, uint32_t reg, uint32_t value) { in write_config_word() argument
A Dtype1.cpp83 int pci_type1::read_config_byte(const pci_location_t state, uint32_t reg, uint8_t *value) { in read_config_byte() argument
84 …LTRACEF_LEVEL(2, "state bus %#hhx dev %#hhx %#hhx reg %#x\n", state.bus, state.dev, state.fn, reg); in read_config_byte()
85 *value = type1_read_byte(state.bus, state.dev, state.fn, reg); in read_config_byte()
89 int pci_type1::read_config_half(const pci_location_t state, uint32_t reg, uint16_t *value) { in read_config_half() argument
90 …LTRACEF_LEVEL(2, "state bus %#hhx dev %#hhx %#hhx reg %#x\n", state.bus, state.dev, state.fn, reg); in read_config_half()
91 *value = type1_read_half(state.bus, state.dev, state.fn, reg); in read_config_half()
95 int pci_type1::read_config_word(const pci_location_t state, uint32_t reg, uint32_t *value) { in read_config_word() argument
96 …LTRACEF_LEVEL(2, "state bus %#hhx dev %#hhx %#hhx reg %#x\n", state.bus, state.dev, state.fn, reg); in read_config_word()
97 *value = type1_read_word(state.bus, state.dev, state.fn, reg); in read_config_word()
A Dbios32.h23 virtual int read_config_byte(pci_location_t state, uint32_t reg, uint8_t *value) override;
24 virtual int read_config_half(pci_location_t state, uint32_t reg, uint16_t *value) override;
25 virtual int read_config_word(pci_location_t state, uint32_t reg, uint32_t *value) override;
27 virtual int write_config_byte(pci_location_t state, uint32_t reg, uint8_t value) override;
28 virtual int write_config_half(pci_location_t state, uint32_t reg, uint16_t value) override;
29 virtual int write_config_word(pci_location_t state, uint32_t reg, uint32_t value) override;
A Decam.h20 int read_config_byte(pci_location_t state, uint32_t reg, uint8_t *value) override;
21 int read_config_half(pci_location_t state, uint32_t reg, uint16_t *value) override;
22 int read_config_word(pci_location_t state, uint32_t reg, uint32_t *value) override;
23 int write_config_byte(pci_location_t state, uint32_t reg, uint8_t value) override;
24 int write_config_half(pci_location_t state, uint32_t reg, uint16_t value) override;
25 int write_config_word(pci_location_t state, uint32_t reg, uint32_t value) override;
A Dtype1.h21 int read_config_byte(pci_location_t state, uint32_t reg, uint8_t *value) override;
22 int read_config_half(pci_location_t state, uint32_t reg, uint16_t *value) override;
23 int read_config_word(pci_location_t state, uint32_t reg, uint32_t *value) override;
A Dbios32.cpp195 int pci_bios32::read_config_byte(const pci_location_t state, uint32_t reg, uint8_t *value) { in read_config_byte() argument
210 "D"(reg), in read_config_byte()
217 int pci_bios32::read_config_half(const pci_location_t state, uint32_t reg, uint16_t *value) { in read_config_half() argument
232 "D"(reg), in read_config_half()
239 int pci_bios32::read_config_word(const pci_location_t state, uint32_t reg, uint32_t *value) { in read_config_word() argument
254 "D"(reg), in read_config_word()
261 int pci_bios32::write_config_byte(const pci_location_t state, uint32_t reg, uint8_t value) { in write_config_byte() argument
276 "D"(reg), in write_config_byte()
283 int pci_bios32::write_config_half(const pci_location_t state, uint32_t reg, uint16_t value) { in write_config_half() argument
298 "D"(reg), in write_config_half()
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/dev/include/dev/
A Di2c.h32 status_t i2c_write_reg_bytes(int bus, uint8_t address, uint8_t reg, const uint8_t *val, size_t cnt);
33 status_t i2c_read_reg_bytes(int bus, uint8_t address, uint8_t reg, uint8_t *val, size_t cnt);
35 static inline status_t i2c_write_reg(int bus, uint8_t address, uint8_t reg, uint8_t val) { in i2c_write_reg() argument
36 return i2c_write_reg_bytes(bus, address, reg, &val, 1); in i2c_write_reg()
39 static inline status_t i2c_read_reg(int bus, uint8_t address, uint8_t reg, uint8_t *val) { in i2c_read_reg() argument
40 return i2c_read_reg_bytes(bus, address, reg, val, 1); in i2c_read_reg()
/dev/net/smc91c96/
A Dsmc91c96.c22 #define SMC_REG16(reg) ((volatile uint16_t *)(smc91c96_base + (reg))) argument
23 #define SMC_REG8(reg) ((volatile uint8_t *)(smc91c96_base + (reg))) argument
/dev/timer/arm_generic/
A Darm_generic_timer.c45 #define READ_TIMER_REG32(reg) ARM64_READ_SYSREG(reg) argument
46 #define READ_TIMER_REG64(reg) ARM64_READ_SYSREG(reg) argument
47 #define WRITE_TIMER_REG32(reg, val) ARM64_WRITE_SYSREG(reg, val) argument
48 #define WRITE_TIMER_REG64(reg, val) ARM64_WRITE_SYSREG(reg, val) argument
70 #define READ_TIMER_REG32(reg) \ argument
73 __asm__ volatile("mrc p15, 0, %0, c14, " reg : "=r" (_val)); \
77 #define READ_TIMER_REG64(reg) \ argument
84 #define WRITE_TIMER_REG32(reg, val) \ argument
86 __asm__ volatile("mcr p15, 0, %0, c14, " reg :: "r" (val)); \
90 #define WRITE_TIMER_REG64(reg, val) \ argument
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/dev/include/dev/class/
A Di2c.h20 status_t (*write_reg)(struct device *dev, uint8_t addr, uint8_t reg, uint8_t value);
21 status_t (*read_reg)(struct device *dev, uint8_t addr, uint8_t reg, void *value);
28 status_t class_i2c_write_reg(struct device *dev, uint8_t addr, uint8_t reg, uint8_t value);
29 status_t class_i2c_read_reg(struct device *dev, uint8_t addr, uint8_t reg, void *value);
/dev/interrupt/arm_gic/
A Darm_gic.c287 gicreg_write32(0, GICD_IGROUPR(reg), gicd_igroupr[reg]); in arm_gic_init()
295 int reg = irq / 32; in arm_gic_set_secure_locked() local
302 gicreg_write32(0, GICD_IGROUPR(reg), (gicd_igroupr[reg] &= ~mask)); in arm_gic_set_secure_locked()
304 gicreg_write32(0, GICD_IGROUPR(reg), (gicd_igroupr[reg] |= mask)); in arm_gic_set_secure_locked()
306 irq, secure, reg, gicreg_read32(0, GICD_IGROUPR(reg))); in arm_gic_set_secure_locked()
312 u_int reg = irq / 4; in arm_gic_set_target_locked() local
322 gicreg_write32(0, GICD_ITARGETSR(reg), (gicd_itargetsr[reg] = new_val)); in arm_gic_set_target_locked()
324 irq, reg, old_val, new_val, gicreg_read32(0, GICD_ITARGETSR(reg))); in arm_gic_set_target_locked()
330 u_int reg = irq / 4; in arm_gic_get_priority() local
336 u_int reg = irq / 4; in arm_gic_set_priority_locked() local
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/dev/class/
A Di2c_api.c34 status_t class_i2c_write_reg(struct device *dev, uint8_t addr, uint8_t reg, uint8_t value) { in class_i2c_write_reg() argument
40 return ops->write_reg(dev, addr, reg, value); in class_i2c_write_reg()
45 status_t class_i2c_read_reg(struct device *dev, uint8_t addr, uint8_t reg, void *value) { in class_i2c_read_reg() argument
51 return ops->read_reg(dev, addr, reg, value); in class_i2c_read_reg()
/dev/bus/pci/include/dev/bus/
A Dpci.h52 status_t pci_read_config_byte(pci_location_t state, uint32_t reg, uint8_t *value);
53 status_t pci_read_config_half(pci_location_t state, uint32_t reg, uint16_t *value);
54 status_t pci_read_config_word(pci_location_t state, uint32_t reg, uint32_t *value);
56 status_t pci_write_config_byte(pci_location_t state, uint32_t reg, uint8_t value);
57 status_t pci_write_config_half(pci_location_t state, uint32_t reg, uint16_t value);
58 status_t pci_write_config_word(pci_location_t state, uint32_t reg, uint32_t value);
/dev/gpio_i2c/
A Dgpio_i2c.c130 const uint8_t *reg, in gpio_i2c_tx_common() argument
143 if ((NULL != reg) && !send_byte(i, *reg)) in gpio_i2c_tx_common()
160 const uint8_t *reg, in gpio_i2c_rx_common() argument
172 if (!send_byte(i, address | (!reg ? 0x1 : 0x0))) in gpio_i2c_rx_common()
175 if (NULL != reg) { in gpio_i2c_rx_common()
176 if (!send_byte(i, *reg)) in gpio_i2c_rx_common()
239 status_t gpio_i2c_write_reg_bytes(int bus, uint8_t address, uint8_t reg, const uint8_t *buf, size_t… in gpio_i2c_write_reg_bytes() argument
244 return gpio_i2c_tx_common(s, address, &reg, buf, cnt); in gpio_i2c_write_reg_bytes()
247 status_t gpio_i2c_read_reg_bytes(int bus, uint8_t address, uint8_t reg, uint8_t *buf, size_t cnt) { in gpio_i2c_read_reg_bytes() argument
253 return gpio_i2c_rx_common(s, address, &reg, buf, cnt); in gpio_i2c_read_reg_bytes()
/dev/bus/pci/
A Dpci.cpp44 status_t pci_read_config_byte(const pci_location_t state, uint32_t reg, uint8_t *value) { in pci_read_config_byte() argument
49 int res = pcib->read_config_byte(state, reg, value); in pci_read_config_byte()
53 status_t pci_read_config_half(const pci_location_t state, uint32_t reg, uint16_t *value) { in pci_read_config_half() argument
58 int res = pcib->read_config_half(state, reg, value); in pci_read_config_half()
63 status_t pci_read_config_word(const pci_location_t state, uint32_t reg, uint32_t *value) { in pci_read_config_word() argument
68 int res = pcib->read_config_word(state, reg, value); in pci_read_config_word()
73 status_t pci_write_config_byte(const pci_location_t state, uint32_t reg, uint8_t value) { in pci_write_config_byte() argument
78 int res = pcib->write_config_byte(state, reg, value); in pci_write_config_byte()
83 status_t pci_write_config_half(const pci_location_t state, uint32_t reg, uint16_t value) { in pci_write_config_half() argument
88 int res = pcib->write_config_half(state, reg, value); in pci_write_config_half()
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/dev/cache/pl310/
A Dpl310.c27 #define PL310_REG(reg) (*REG32(PL310_BASE + (reg))) argument
150 #define PL310_LOOP_BODY(reg) \ argument
165 PL310_REG(reg) = pa; \
/dev/timer/arm_cortex_a9/
A Darm_cortex_a9_timer.c36 #define TIMREG(reg) (*REG32(scu_control_base + PRIV_TIMER_OFFSET + (reg))) argument
47 #define GTIMREG(reg) (*REG32(scu_control_base + GLOBAL_TIMER_OFFSET + (reg))) argument
/dev/net/e1000/
A De1000.cpp79 uint32_t read_reg(e1000_reg reg);
80 void write_reg(e1000_reg reg, uint32_t val);
121 uint32_t e1000::read_reg(e1000_reg reg) { in read_reg() argument
122 volatile uint32_t *r = (volatile uint32_t *)((uintptr_t)bar0_regs_ + (size_t)reg); in read_reg()
127 void e1000::write_reg(e1000_reg reg, uint32_t val) { in write_reg() argument
128 volatile uint32_t *r = (volatile uint32_t *)((uintptr_t)bar0_regs_ + (size_t)reg); in write_reg()

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